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april 2002 1 ? 2002 actel corporation advanced v0.6 proasic plus ? family flash fpgas features and benefits high capacity 150,000 to 1 million system gates 36k to 198 kbits of two-port sram 106 to 712 user i/os performance 3.3v, 32-bit pci (up to 50 mhz) internal system performance up to 350 mhz external system performance up to 150 mhz reprogrammable flash technology 0.22 4 lm flash-based cmos process live at power up, single-chip solution no configuration device required retains programmed design during power-down/ power-up cycles secure programming the industry ? s most effective security key prevents read back of programming bit stream low power low impedance flash switches segmented hierarchical routing structure small, efficient, configurable (combinatorial or sequential) logic cells high performance routing hierarchy ultra fast local and long line network high speed very long line network high performance, low skew, splitable global network 100% routability and utilization i/o schmitt trigger option on every input mixed 2.5v/3.3v support with individually-selectable voltage and slew rate bidirectional global i/os compliance with pci specification revision 2.2 boundary-scan test ieee std. 1149.1 (jtag) compliant pin compatible packages across proasic plus family unique clock conditioning circuitry two integrated plls (1.5 to 240 mhz input and output ranges) pll with flexible phase, multiply/divide and delay capabilities internal and/or external dynamic pll configuration two lvpecl differential pairs for clock or data inputs standard fpga and asic design flow flexibility with choice of industry-standard front-end tools efficient design through front-end timing and gate optimization isp support in-system programming (isp) via jtag port srams and fifos netlist generation ensures optimal usage of embedded memory blocks synchronous and asynchronous operation of 24 ram and fifo configurations (up to 150 mhz) proasic plus product profile device apa150 apa300 apa450 apa600 apa750 apa1000 maximum system gates 150,000 300,000 450,000 600,000 750,000 1,000,000 maximum registers 6,144 8,192 12,288 21,504 32,768 56,320 embedded ram bits 36k 72k 108k 126k 144k 198k embedded ram blocks (256 x 9) 16 32 48 56 64 88 lvpecl 222222 pll 222222 global networks 444444 maximum clocks 32 32 48 56 64 88 maximum user i/os 242 304 356 456 642 712 jtag yes yes yes yes yes yes pci yes yes yes yes yes yes package (by pin count) pqfp pbga fbga 208 456 144, 256 208 456 144, 256 208 456 144, 256 208 456 256, 676 208 456 676, 896 208 456 896, 1152
proasic plus family flash fpgas 2 advanced v0.6 general description the proasicplus family of devices offers enhanced performance over actel ? s proasic family. it combines the advantages of asics with the benefits of programmable devices through nonvolatile flash technology. this enables engineers to create high-density systems using existing asic or fpga design flows and tools. in addition, the proasicplus family offers a unique clock conditioning circuit based on two on-board phase lock loops (plls). the family offers up to 1 million system gates, supported with up to 198 kbits of 2-port sram and up to 712 user i/os, all providing 50 mhz pci performance. advantages to the designer extend beyond performance. four levels of routing hierarchy simplify routing, while the use of flash technology allows all functionality to be live at power up, unlike sram-based fpgas. no external boot prom is required to support device programming. while on-board security mechanisms prevent all access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. the device ? s architecture mitigates the complexity of asic migration at higher user volume. this makes proasicplus a cost-effective solution for applications in the networking, communications, computing, and avionics markets. the proasicplus family achieves its nonvolatility and reprogrammability through an advanced flash-based 0.22m lvcmos process with four-layer metal. standard cmos design techniques are used to implement logic and control functions, including the plls and lvpecl inputs. the result is predictable performance fully compatible with gate arrays. the proasicplus architecture provides granularity comparable to gate arrays. the device core consists of a sea-of-tilestm. each tile can be configured as a flip-flop, latch, or 3-input/1-output logic function by programming the appropriate flash switches. the combination of fine granularity, flexible routing resources, and abundant flash switches allow 100% utilization and over 95% routability for highly congested designs. tiles and larger functions are interconnected through a 4-level routing hierarchy. embedded 2-port sram blocks with built-in fifo/ram control logic can have user-defined depth and width. users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. the clock conditioning circuitry is unique. devices contain two clock conditioning blocks, each with a pll core, delay lines, phase shifts (0 , 90 , 180 , 270 ), and clock multipliers/dividers. in short, this is all the circuitry needed to provide bidirectional access to the pll, and operation up to 240 mhz. the pll block contains four programmable frequency dividers which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. the clock conditioning circuit also delays or advances the incoming reference clock up to 4ns (in increments of 0.25ns). the pll can be configured internally or externally during operation without redesigning or reprogramming the part. in addition to the pll, there are two lvpecl differential input pairs to accommodate high speed clock and data inputs. to support customers ? needs for more comprehensive, lower cost board-level testing, actel ? s proasic plus devices are fully compatible with ieee standard 1149.1 for test access port and boundary-scan test architecture. for more details on the flash fpga implementation please refer to the ? boundary scan ? section on page 12 . proasic plus devices are available in a variety of high-performance plastic packages. those packages, and the performance features discussed above, are described in more detail in the following sections of this document: ? features and benefits ? section on page 1 ? proasicplus architecture ? section on page 5 ? routing resources ? section on page 6 ? clock trees ? section on page 9 ? input/output blocks ? section on page 10 ? lvpecl input pads ? section on page 11 ? boundary scan ? section on page 12 ? user security ? section on page 14 ? embedded memory floorplan ? section on page 14 ? design environment ? section on page 17 ? package thermal characteristics ? section on page 19 ? operating conditions ? section on page 22 ? dc electrical specifications (v ddp = 2.5v +/-0.2v) ? section on page 23 ? page 25 ? ac specifications (3.3v pci revision 2.2 operation) ? section on page 26 ? clock conditioning circuit ? section on page 27 ? embedded memory specifications ? section on page 35 ? package pin assignments ? section on page 55 ? page 109 for more information concerning in-system programming with proasic plus , refer to the application note, performing internal in-system programming using actel?s proasic plus devices . http://www.actel.com/appnotes/paplusispan.pdf
advanced v0.6 3 proasic plus family flash fpgas ordering information product plan apa1000 fg _ part number speed grade blank = standard speed = tbd 1 package type pq = plastic quad flat pack fg = fineball grid array pb = plastic ball grid array 1152 es package lead count application (ambient temperature range) blank = commercial (0 to +70? c) i = industrial (-40 to +85? c) pp = pre-production es = engineering silicon (room temperature only) 150,000 equivalent system gates apa150 = apa450 apa600 apa750 apa1000 450,000 equivalent system gates 600,000 equivalent system gates 750,000 equivalent system gates 1,000,000 equivalent system gates apa300 300,000 equivalent system gates = = = = = speed grade application std ?1 c i apa150 device 208-pin plastic quad flat pack (pqfp) p p p p 456-pin plastic ball grid array (pbga) p p p p 144-pin fine ball grid array (fbga) p p p p 256-pin fine ball grid array (fbga) p p p p apa300 device 208-pin plastic quad flat pack (pqfp) p p p p 456-pin plastic ball grid array (pbga) p p p p 144-pin fine ball grid array (fbga) p p p p 256-pin fine ball grid array (fbga) p p p p apa450 device 208-pin plastic quad flat pack (pqfp) p p p p 456-pin plastic ball grid array (pbga) p p p p 144-pin fine ball grid array (fbga) p p p p 256-pin fine ball grid array (fbga) p p p p apa600 device 208-pin plastic quad flat pack (pqfp) p p p p 456-pin plastic ball grid array (pbga) p p p p 256-pin fine ball grid array (fbga) p p p p 676-pin fine ball grid array (fbga) p p p p apa750 device 208-pin plastic quad flat pack (pqfp) ? ppp 456-pin fine ball grid array (pbga) ? ppp 676-pin fine ball grid array (fbga) p p p p 896-pin plastic ball grid array (fbga) p p p p apa1000 device 208-pin plastic quad flat pack (pqfp) ? ppp 456-pin plastic ball grid array (pbga) ? ppp 896-pin plastic ball grid array (fbga) p p p p 1152-pin plastic ball grid array (fbga) p p p p applications: c = commercial availability: p =planned i=industrial ? = limited availability ? contact your actel sales representative for the latest availability information.
proasic plus family flash fpgas 4 advanced v0.6 plastic device resources user i/os device pqfp 208-pin pbga 456-pin fbga 144-pin fbga 256-pin fbga 676-pin fbga 896-pin fbga 1152-pin apa150 158 242 100 186 apa300 158 290 100 186 apa450 158 344 100 186 apa600 158 356 186 454 apa750 158 356 454 562 apa1000 158 356 642 712 package definitions pqfp = plastic quad flat pack, pbga = plastic ball grid array, fbga = fine ball grid array
advanced v0.6 5 proasic plus family flash fpgas proasic plus architecture the proprietary proasic plus architecture provides granularity comparable to gate arrays. the proasic plus device core ( figure 1 ) consists of a sea-of-tiles ? . each tile can be configured as a 3-input logic function (e.g., nand gate, d-flip-flop, etc.) by programming the appropriate flash switch interconnections ( figure 2 on page 6 and figure 3 on page 6 ). tiles and larger functions are connected with any of the four levels of routing hierarchy. flash cells are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. maximum core utilization is possible for virtually any design. proasic plus devices also contain embedded two-port sram blocks with built-in fifo/ram control logic. programming options include synchronous or asynchronous operation, two-port ram configurations, user defined depth and width, and parity generation or checking. table 3 on page 14 lists the 24 basic memory configurations. flash switch unlike sram fpgas, proasic plus uses a live on power-up isp flash switch as its programming element. in the proasic plus flash switch , two transistors share the floating gate, which stores the programming information. one is the sensing transistor, which is only used for writing and verification of the floating gate voltage. the other is the switching transistor. it can be used in the architecture to connect/separate routing nets or to configure logic. it is also used to erase the floating gate ( figure 2 on page 6 ). logic tile the logic tile cell ( figure 3 on page 6 ) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra fast local and efficient long line routing resources). any three-input one-output logic function, except a three input xor, can be configured as one tile. the tile can be configured as a latch with clear or set or as a flip-flop with clear or set. thus the tiles can flexibly map logic and sequential gates of a design. figure 1 ? the proasic plus device architecture 256x9 two-port sram or fifo block logic tile
proasic plus family flash fpgas 6 advanced v0.6 routing resources the routing structure of the proasic plus devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra fast local resources, efficient long line resources, high speed very long line resources, and high performance global networks. the ultra fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles ( figure 4 on page 7 ). the efficient long line resources provide routing for longer distances and higher fanout connections. these resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire proasic plus device ( figure 5 on page 7 ). each tile can drive signals onto the efficient long line resources, which can, in turn, access every input of every tile. active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. the high speed very long line resources which span the entire device with minimal delay, are used to route very long or very high fanout nets. ( figure 6 on page 8 ). the high performance global networks are low skew, high fanout nets that are accessible from external pins or from internal logic ( figure 7 on page 9 ). these nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. the global networks are implemented as clock trees, and signals can be introduced at any junction. these can be employed hierarchically, with signals accessing every input on all tiles. figure 2 flash switch figure 3 core logic tile s col d col switch in switch out word floating gate sensing switching local routing in 1 in 2 (clk) in 3 (reset) efficient long line routing
advanced v0.6 7 proasic plus family flash fpgas figure 4 ultra fast local resources figure 5 efficient long line resources l l l l l l inputs o utput ultra fast local lines (connects a tile to the adjacent tile, i/o buffer, or memory block) l l l l lllll l lllll l l llll l l llll l lllll logic cell spans 1 tile spans 2 tiles spans 4 tile spans 1 tile spans 2 tiles spans 4 tile logic tile
proasic plus family flash fpgas 8 advanced v0.6 figure 6 high speed very long line resources pad ring pad ring pad ring i/o ring i/o ring high speed very long line resouces
advanced v0.6 9 proasic plus family flash fpgas clock resources the proasic plus family offers powerful and flexible control of circuit timing through the use of analog circuitry. each chip has two clock conditioning blocks, containing a 240 mhz phase lock loop (pll) core, delay lines, phase shifter(0 , 90 , 180 , 270 ), clock multiplier/dividers and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the pll). this permits the pll block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). this circuitry is discussed in more detail later in the data sheet. clock trees one of the main architectural benefits of proasic plus is the set of power and delay friendly global networks. proasic plus offers 4 global trees. each of these trees is based on a network of spines and ribs that reach all the tiles in their regions ( figure 7 ). this flexible clock tree architecture allows users to map up to 88 different internal/external clocks in an apa1000 device. details on the clock spines and various numbers of the family are given in table 1 on page 10 . the flexible use of the proasic plus clock spine allows the designer to cope with several design requirements. users implementing clock resource intensive applications can easily route external or gated internal clocks using global routing spines. users can also drastically reduce delay penalties and save buffering resources by mapping critical high-fanout nets to spines. for design hints on using these features, refer to actel ? s efficient use of proasic clock trees application note. note: this figure shows routing for only one global path. figure 7 high performance global network pad ring pad ring pad ring i/o ring i/o ring global pads global pads high performace global network low skew global networks global spine global ribs scope of spine
proasic plus family flash fpgas 10 advanced v0.6 input/output blocks to meet complex system demands, the proasic plus family offers devices with a large number of user i/o pins, up to 712 on the apa1000. if the i/o pad is powered at 3.3v, each i/o can be selectively configured at the 2.5v and 3.3v threshold levels. table 2 shows the available supply voltage configurations (the pll block uses an independent 2.5v supply). figure 8 illustrates i/o interfaces with global networks. all i/os include esd protection circuits. each i/o has been tested to 2000v to the human body model (per mil-std-883, method 3015). six or seven standard i/o pads are grouped with a gnd pad and either a v dd or v ddp pad. two reference bias signals ring the chip. one protects the cascaded output drivers while the other creates a virtual v dd supply for the i/o ring. table 1 number of clock spines apa150 apa300 apa450 apa600 apa750 apa1000 top spine height 24 32 32 48 64 80 tiles in each top spine 768 1,024 1,024 1,536 2,048 2,560 bottom spine height 24 32 32 48 64 80 tiles in each bottom spine 768 1,024 1,024 1,536 2,048 2,560 global clock networks (trees) 4 4 4 4 4 4 clock spines/tree 8 8 12141622 total spines 32 32 48 56 64 88 total tiles 6,144 8,192 12,288 21,504 32,768 56,320 table 2 proasic plus power supply voltages v ddp 2.5v 3.3v input tolerance 2.5v 3.3v, 2.5v output drive 2.5v 3.3v, 2.5v notes: 1. v dd is always 2.5v. 2. there is no requirement for power-supply sequencing for proasic plus devices. figure 8 proasic plus global i/o scheme with multiplexed global pads pa d pa d pa d pa d pa d standard i/o pad cell standard i/o pad cell standard i/o pad cell global mux driver global mux driver pecl input pad cell i/o tile x i/o tile a i/o tile ga i/o tile gb i/o tile b i/o gl gl ppecl gl gl npecl hc hc pc<0:4> p<1,2> p<0> pc<0:4> p<1,2> p<0> pc<0:4> p<1,2> p<0> pc<0:4> p<1,2> p<0> pc<0:4> p<1,2> p<0>
advanced v0.6 11 proasic plus family flash fpgas i/o pads are fully configurable to provide the maximum flexibility and speed. each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer ( figure 9 ). i/o pads configured as inputs have the following features: individually selectable 2.5v or 3.3v threshold levels 1 optional pull-up resistor i/o pads configured as outputs have the following features: individually selectable 2.5v or 3.3v compliant output signals 1 3.3v pci compliant ability to drive lvttl and lvcmos levels selectable drive strengths selectable slew rates tristate i/o pads configured as bidirectional buffers have the following features: individually selectable 2.5v or 3.3v output signals and threshold levels 1 3.3v pci compliant optional pull-up resistor optionally configurable as schmitt trigger input 2 selectable drive strengths selectable slew rates tristate lvpecl input pads in addition to standard i/o pads and power pads, proasic plus devices have a pecl input pad at each end of each of the global mux lines, along with avdd and agnd pins to power the pll block. the pecl input pad cell is different from the standard i/o cell. it is operated from v dd only. since it is exclusively an input, it requires no output signal, output enable signal or output configuration bits. as a special high-speed differential input, it also does not require pull ups. the pecl pad cell ( figure 10 ) consists of an input buffer (containing a low voltage differential amplifier, whose power is enabled by the pc<0> and cl<1> signals, and a cascaded buffer), and a signal and its compliment (ppecl and npecl). the pecl pad cell compares voltages on the ppecl pad and the npecl pad and sends the results to the global mux over the p<0> wire. this high speed, low skew output essentially controls the clock conditioning circuit. 1. if pads are configured for 2.5v operation, they are compliant with 2.5v level signals as defined by jedec jesd 8-5. if pads are configured for 3.3v operation, they are compliant with the standard as defined by jedec jesd 8-a (lvttl and lvcmos). 2. the schmitt trigger input option can be configured as an input only, not a bidirectional buffer. this input type may be slower than a standard input under certain conditions and has typical hysteresis of about 0.3v. figure 9 i/o block schematic representation 3.3v/2.5v signal control pull-up control pad y en a 3.3v/2.5v signal control drive strength and slew rate control figure 10 high speed pecl pad cell block diagram cl<1> ppecl pad + esd protection + clamp npecl pad + esd protection + clamp input buffer p<0> pc<0> ppecl pa d npecl pa d core & global mux
proasic plus family flash fpgas 12 advanced v0.6 boundary scan proasic plus devices are compatible with ieee standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. the basic proasic plus boundary-scan logic circuit is composed of the tap (test access port), tap controller, test data registers, and instruction register ( figure 11 ). this circuit supports all mandatory ieee 1149.1 instructions (extest, sample/preload and bypass), the optional idcode instructions and private instructions used for device programming and factory testing. each test section is accessed through the tap, which has five associated pins: tck (test clock input), tdi, and tdo (test data input and output), tms (test mode selector) and trst (test reset input). tms, tdi and trst are equipped with pull-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundary-scan test usage. the tap controller is a four-bit state machine (16 states) that operates as shown in figure 12 on page 13 . the ? 1 ? s and ? 0 ? s represent the values that must be present at tms at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. figure 11 proasic plus jtag boundary scan test logic circuit device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers
advanced v0.6 13 proasic plus family flash fpgas the tap controller receives two control inputs (tms and tck) and generates control and clock signals for the rest of the test logic architecture. on power up, the tap controller enters the test-logic-reset state. to guarantee a reset of the controller from any of the possible states, tms must remain high for five tck cycles. the trst pin may also be used to asynchronously place the tap controller in the test-logic-reset state. proasic plus devices support three types of test data registers: bypass, device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device. this speeds up test data transfer to other devices in a test data path. the 32-bit device identification register is a shift register with four fields (lsb, id number, part number and version). the boundary-scan register observes and controls the state of each i/o pin. each i/o cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pins. the serial pins are used to serially connect all the boundary-scan register cells in a device into a boundary scan register chain which starts at the tdi pin and ends at the tdo pin. the parallel ports are connected to the internal core logic tile and the input, output, and control ports of an i/o buffer to capture and load data into the register to control or observe the logic state of each i/o. figure 12 tap controller state diagram test-logic reset run-test/ idle select-dr- scan capture-dr shift-dr exit-dr pause-dr exit2-dr update-dr select-ir- scan capture-ir shift-ir exit-ir pause-ir exit2-ir update-ir 1 1 1 0 1 0 00 1 1 00 00 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
proasic plus family flash fpgas 14 advanced v0.6 user security the proasic plus devices have read-protect bits that, once programmed, block the entire programmed contents from being read externally. if locked, the user can only reprogram the device using the security key. this protects it from being read back and duplicated. since programmed data is stored in nonvolatile memory cells (which are actually very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. this approach is further hampered by the placement of the memory cells, beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). this is the highest security provided in the industry. for more information, refer to actel ? s design security in nonvolatile flash and antifuse fpgas white paper. embedded memory floorplan the embedded memory is located across the top of the device (see figure 1 on page 5 ) in 256x9 blocks. depending upon the device, up to 88 blocks are available to support a variety of memory configurations. each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. a single memory configuration cannot include blocks from both the top and bottom memory locations. embedded memory configurations the embedded memory in the proasic plus family provides great configuration flexibility. other programmable vendors typically use single port memories that can only be transformed into two-port memories by sacrificing half the memory. each proasic plus block is designed and optimized as a two-port memory (1 read, 1 write). this provides 198k bits of total memory for two-port and single port usage in the apa1000 device. each memory can be configured as fifo or sram, with independent selection of synchronous or asynchronous read and write ports ( table 3 ). additional characteristics include programmable flags as well as parity checking and generation. figure 13 on page 15 and figure 14 on page 16 show the block diagrams of the basic sram and fifo blocks. these memories are designed to operate at up to 150 mhz when operated individually. each block contains a 256 word, 9-bit wide (1 read, 1 write) memory. the memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories ( figure 15 on page 16 ). this provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1024. refer to the actel ? s macro library guide for more information. figure 16 on page 17 gives an example of optimal memory usage. ten blocks with 23,040 bits have been used to generate three memories of various widths and depths. figure 17 on page 17 shows how memory can be used in parallel to create extra read ports. in this example, using only 10 of the 88 available blocks of the apa1000 yields an effective 6,912 bits of multiple port memories. the actel actgen software facilitates building wider and deeper memories for optimal memory usage. table 3 basic memory configurations type write access read access parity library cell name ram asynchronous asynchronous checked ram256x9aa ram asynchronous asynchronous generated ram256x9aap ram asynchronous synchronous transparent checked ram256x9ast ram asynchronous synchronous transparent generated ram256x9astp ram asynchronous synchronous pipelined checked ram256x9asr ram asynchronous synchronous pipelined generated ram256x9asrp ram synchronous asynchronous checked ram256x9sa ram synchronous asynchronous generated ram256xsap ram synchronous synchronous transparent checked ram256x9sst ram synchronous synchronous transparent generated ram256x9sstp ram synchronous synchronous pipelined checked ram256x9ssr ram synchronous synchronous pipelined generated ram256x9ssrp fifo asynchronous asynchronous checked fifo256x9aa fifo asynchronous asynchronous generated fifo256x9aap fifo asynchronous synchronous transparent checked fifo256x9ast fifo asynchronous synchronous transparent generated fifo256x9astp
advanced v0.6 15 proasic plus family flash fpgas fifo asynchronous synchronous pipelined checked fifo256x9asr fifo asynchronous synchronous pipelined generated fifo256x9asrp fifo synchronous asynchronous checked fifo256x9sa fifo synchronous asynchronous generated fifo256x9sap fifo synchronous synchronous transparent checked fifo256x9sst fifo synchronous synchronous transparent generated fifo256x9sstp fifo synchronous synchronous pipelined checked fifo256x9ssr fifo synchronous synchronous pipelined generated fifo256x9ssrp note: for memory block interface signal definitions, see table 4 on page 35 figure 13 example sram block diagrams table 3 basic memory configurations (continued) type write access read access parity library cell name sram (256 x 9) sync write & sync read ports di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb rdb wblkb rblkb wclks rclks rpe parodd sram (256 x 9) async write & async read ports di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb wblkb rdb rblkb parodd wpe rpe wpe sram (256 x 9) sync write & async read ports di <0:8> do <0:8> waddr <0:7> wrb rdb wblkb rblkb wclks rpe parodd wpe raddr <0:7> parodd sram (256 x 9) async write & sync read ports di <0:8> do <0:8> raddr <0:7> waddr <0:7> wrb rdb wblkb rblkb rclks rpe wpe
proasic plus family flash fpgas 16 advanced v0.6 note: for memory block fifo signal definitions, see table 5 on page 46 . figure 14 basic fifo block diagrams figure 15 apa1000 memory block architecture fifo (256 x 9) sync write & sync read ports level<0:7> do <0:8> di<0:8> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth wclks rclks fifo (256 x 9) sync write & async read ports di <0:8> do <0:8> level <0:7> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth wclks fifo (256 x 9) async write & async.read ports di <0:8> do <0:8> level <0:7> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth fifo (256 x 9) async write & sync read ports di <0:8> do <0:8> level <0:7> wrb rdb wblkb rblkb rpe parodd wpe lgdep<0:2> full empty eqth geqth rclks reset reset word depth word width 88 blocks 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9 256 9
advanced v0.6 17 proasic plus family flash fpgas design environment proasic plus devices are supported by actel ? s designer series, as well as third party cae tools. unlike some fpga vendors, no special hdl design techniques are needed when using the standard vhdl or verilog hdl descriptions. as a result, designers may utilize technology independent of hdl code for proasic plus devices. this feature and the asic-like design flow ensure a seamless transition to an asic implementation, if desired ( figure 18 on page 18 ). actgen, included in actel ? s designer series, can be used to automatically generate memories based on user inputs. the design engineer can select the depth and width, usage of parity generation or check, and synchronous or asynchronous functionality of the ports. for a synchronous read port, the user can choose whether the output is pipelined or transparent. designer allows any bit width up to 252. however, when an intermediate bit width, such as 16 bits, is chosen, the remaining two bits are not accessible for other memories. actel ? s designer also enables optimal memory stacking in 256 word increments. however, any word depth may be combined for up to 22,528 words. actgen also allows the user to generate distributed memory. figure 16 example showing memories with different widths and depths figure 17 multiport memory usage word depth word width 1,024 words x 9 bits, 1 read, 1 write 512 words x 18 bits, 1 read, 1 write 256 words x 18 bits, 1 read, 1 write total memory blocks used = 10 total memory bits = 23,040 256 256 256 256 9 256 256 9 9 256 99 256 9 256 9 1,024 words x 9 bits, 4 read, 1 write 256 words x 9 bits, 2 read, 1 write total memory blocks used = 10 total memory bits = 6,912 word depth word width write port write port read ports 9 9 read ports
proasic plus family flash fpgas 18 advanced v0.6 place and route is also performed by actel ? s designer software. available for unix workstations and pc platforms, designer accepts standard netlists in verilog, vhdl, and edif formats, performs place and route of the design into the selected device, and provides postlayout delay information for back-annotation simulation and static timing analysis. actgen provides all the software needed for configuration of the pll clock conditioning circuit. while the pll has no placement mobility, actgen allows users to use placement and routing floorplan constraints hierarchically, in order to more easily and efficiently explore floorplan alternatives. this allows the power of the pll circuitry to be utilized with minimal top level timing loop iterations. actel ? s designer can also generate the bsdl (boundary-scan description language) files required for documenting the ieee 1149.1 components which can be used by automatic test equipment software. actel ? s designer also contains the necessary information for the placing, routing, and configuration of the clock conditioning circuit. once the design is finalized, the programming bitstream is downloaded into the device programmer for programming the proasic plus part. proasic plus devices can be programmed with the silicon sculptor ii and flash pro programmers. additionally, in-system programming is available. for details on proasic plus programming, refer to the application note, performing internal in-system programming using actel ? s proasic plus devices . figure 18 design flow design creation/verification design implementation synthesis tool high-level design (verilog or vhdl) designer (p&r tool) p&r user constraints synthesis library programming silicon sculptor ii flash pro timing libraries simulation library sdf timing file forward constraints programming data timing analyzer timing and simulation backannotation simulation library structural netlist actgen verilog or vhdl simulator verilog or vhdl simulator
advanced v0.6 19 proasic plus family flash fpgas package thermal characteristics the proasic plus family is available in several package types with a range of pin counts. actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package, to the surrounding air. junction-to-ambient thermal resistance is measured in degrees celsius/watt and is represented as theta ja ( ja ). the lower thermal resistance, the more efficiently a package will dissipate heat. a package ? s maximum allowed power (p) is a function of maximum junction temperature (t j ), maximum ambient operating temperature (t a ), and junction-to-ambient thermal resistance ja . maximum junction temperature is the maximum allowable temperature on the active surface of the ic and is 110 c. p is defined as : ja is a function of the rate (in linear feet per minute - lfpm) of airflow in contact with the package. when the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. p t j t a ? ja ----------------- = package type pin count jc ja still air ja 300 ft./min units plastic quad flat pack (pqfp) 208 8 30 23 c/w pqfp with heatspreader 208 3.8 20 17 c/w fine ball grid array (fbga) 144 3.8 38.8 26.7 c/w fine ball grid array (fbga) 256 3.0 30 25 c/w plastic ball grid array (pbga) 456 3 18 14.5 c/w fine ball grid array (fbga) 676 3.2 15 11.5 c/w fine ball grid array (fbga) 896 2.0 10.9 7.9 c/w fine ball grid array (fbga) 1152 2.0 11.2 7.0 c/w
proasic plus family flash fpgas 20 advanced v0.6 calculating power dissipation proasic plus device power is calculated with both a static and an active component. the active component is a function of both the number of tiles utilized and the system speed. power dissipation can be calculated using the following formula: p total = p dc + p ac where: p clock , the clock component of power dissipation, is given by p clock = (p1 + p2 * s) * fs where: p storage , the storage-tile component of ac power dissipation, is given by p storage = p5 * ms * fs where: p logic , the logic-tile component of ac power dissipation, is given by p logic = p3 * mc * fs where: p ios , the i/o component of ac power dissipation, is given by p ios = (p4 + c load * v ddp ^2) * p * fp where: finally, p memory , the memory component of ac power consumption, is given by p memory = p6 * n mem * f mem where: p dc = 10 mw p ac =p clock + p storage + p logic + p ios + p memory p1 = 2500 uw/mhz is the basic power consumption of the clock tree normalized per mhz of the clock. p2 = 1.0 uw/mhz is the extra power consumption of the clock tree per storage tile ? also normalized per mhz of the clock s = the number of storage tiles clocked by this clock fs = the clock frequency p5 = 1.0 uw/mhz is the average power consumption of a storage-tile normalized per mhz of its output frequency ms = the number of storage tiles switching during each fs cycle fs = the clock frequency p3 = 3.0 uw/mhz, is the average power consumption of a logic-tile normalized per mhz of its output frequency mc = the number of logic tiles switching during each fs cycle fs = the clock frequency p4 = 60.0 uw/mhz is the average power consumption of an output pad normalized per mhz of its output frequency (internal power-load is not included) c load = the output load p = the number of outputs fp = the average output frequency p6 = 100.0 uw/mhz is the average power consumption of a memory block normalized per mhz of the clock n mem = the number of ram/fifo blocks (1 block = 256 words * 9 bits) f mem = the clock frequency of the memory
advanced v0.6 21 proasic plus family flash fpgas the following is an apa750 example using a shift register design with 13,440 storage tiles and 0 logic tiles. this design has one clock at 10 mhz, and 24 outputs toggling at 5 mhz. we then calculate the various components as follows: p clock => pclock = (p1 + p2 * s) * fs = 159.4 mw p storage => pstorage = p5 * ms * fs = 134.4 mw p logic => p logic = 0 mw p ios fp = 5 mhz => p ios = (p4 + cload * v ddp ^2) * p * fp = 54.1 mw p memory => p memory = 0 mw p ac => 347.9 mw p total p dc + p ac = 357.9mw fs = 10 mhz s = 13,440 ms = 13,440 (in a shift register 100% of storage-tiles are toggling at each clock cycle and fs = 10 mhz) mc = 0 (no logic tile in this shift-register) c load =40 pf v ddp = 3.3 v p=24 n mem = 0 (no ram/fifo in this shift-register) power consumption of an apa device 0 100 200 300 400 500 600 700 800 900 1000 frequency (mhz) power consumption (mw) 20 30 40 50 60 70 80 90 100 120 sram proasic 110 instances of 16-bit binary counters
proasic plus family flash fpgas 22 advanced v0.6 operating conditions absolute maximum ratings parameter condition minimum maximum units supply voltage (v dd )? 0.3 3.0 v supply voltage i/o ring (v ddp ) ? 0.3 4.0 v dc input voltage ? 0.3 v ddp + 0.3 v pci dc input voltage ? 0.5 v ddp + 0.5 v dc input clamp current v in < 0 or v in > v ddp ? 10 +10 ma pecl input voltage 0 2.5 v programming and storage temperature limits product grade programming cycles program retention storage temperature min. max. commercial 100 20 years ? 55 c110 c industrial 100 20 years ? 55 c110 c supply voltages mode v dd v ddp v pp v pn single voltage 2.5v 2.5v 0 v pp 16.5v ? 13.8v v pn 0v mixed voltage 2.5v 3.3v 0 v pp 16.5v ? 13.8v v pn 0v recommended operating conditions parameter symbol limits commercial dc supply voltage (2.5v i/os) v dd & v ddp 2.3v to 2.7v dc supply voltage (mixed 2.5v, 3.3v i/os) v ddp v dd 3.0v to 3.6v 2.3v to 2.7v operating ambient temperature range t a 0 c to 70 c maximum operating junction temperature t j 110 c maximum clock frequency f clock 240 mhz maximum ram frequency f ram 150 mhz industrial dc supply voltage (2.5v i/os) v dd & v ddp 2.3v to 2.7v dc supply voltage (2.5v, 3.3v i/os) v ddp v dd 3.0v to 3.6v 2.3v to 2.7v operating ambient temperature range t a ? 40 c to 85 c maximum operating junction temperature t j 110 c maximum clock frequency f clock 240 mhz maximum ram frequency f ram 150 mhz
advanced v0.6 23 proasic plus family flash fpgas dc electrical specifications (v ddp = 2.5v +/-0.2v) symbol parameter conditions min. typ. max. units v oh output high voltage high drive (ob25lph) low drive (ob25lpl) i oh = ? 6 ma i oh = ? 12 ma i oh = ? 24 ma i oh = ? 4 ma i oh = ? 6 ma i oh = ? 10 ma 2.1 2.0 1.7 2.1 2.0 1.7 v v ol output low voltage high drive (ob25lph) low drive (ob25lpl) i ol = 8 ma i ol = 15 ma i ol = 24 ma i ol = 4 ma i ol = 8 ma i ol = 15 ma 0.2 0.4 0.7 0.2 0.4 0.7 v v ih input high voltage 1.7 v ddp + 0.3 v v il input low voltage ? 0.3 0.7 v r weakpullup weak pull-up resistance (otb25lpu) v in 1.25 10 30 k ? i in input current input current with pull up (v in = v ss ) without pull up (v in = v ss or v dd ) ? 250 ? 10 ? 80 10 ? ? i ddq quiescent supply current (standby) v in = v ss 2 or v dd 5.0 10 ma i oz 3-state output leakage current v oh = v ss or v dd ? 10 10 a i osh output short circuit current high high drive (ob25lph) low drive (ob25lpl) v in = v ss v in = v ss ? 120 ? 100 ma i osl output short circuit current low high drive (ob25lph) low drive (ob25lpl) v in = v ddp v in = v ddp 100 30 ma c i/o i/o pad capacitance 10 pf c clk clock input pad capacitance 10 pf notes: 1. all process conditions. junction temperature: ? 40 to +110 c. 2. no pull-up resistor.
proasic plus family flash fpgas 24 advanced v0.6 dc electrical specifications (v ddp = 3.3v +/-0.3v and v dd 2.5+/-0.2v) symbol parameter conditions min. typ. max. units v oh output high voltage 3.3v i/o, high drive (ob33p) 3.3v i/o, low drive (ob33l) i oh = ? 15 ma i oh = ? 30 ma i oh = ? 7 ma i oh = ? 14 ma 0.9 ? v ddp 2.4 0.9 ? v ddp 2.4 v output high voltage 2.5v i/o, high drive (ob25h) 2.5v i/o, low drive (ob25l) i oh = ? 0.1 ma i oh = ? 0.5 ma i oh = ? 4 ma i oh = ? 0.1 ma i oh = ? 0.5 ma i oh = ? 2.5 ma 2.1 2.0 1.7 2.1 2.0 1.7 v v ol output low voltage 3.3v i/o, high drive (ob33p) 3.3v i/o, low drive (ob33l) i ol = 15 ma i ol = 20 ma i ol = 7 ma i ol = 10 ma 0.1v ddp 0.4 0.1v ddp 0.4 v output low voltage 2.5v i/o, high drive (ob25h) 2.5v i/o, low drive (ob25l) i ol = 7 ma i ol = 14 ma i ol = 28 ma i ol = 5 ma i ol = 10 ma i ol = 15 ma 0.2 0.4 0.7 0.2 0.4 0.7 v v ih input high voltage 3.3v lvttl/lvcmos 2.5v mode 2 1.7 v ddp + 0.3 v ddp + 0.3 v v il input low voltage 3.3v lvttl/lvcmos 2.5v mode 0.3 0.3 0.8 0.7 v r weakpullup weak pull-up resistance (otb33u) v in 1.5 15k 25k k ? r weakpullup weak pull-up resistance (otb25u) v in 1.5 10k 20k k ? i in input current with pull up (v in = v ss ) without pull up (v in = v ss or v dd ) ? 300 ? -10 ? 80 10 ? ? i ddq quiescent supply current (standby) v in = v ss 2 or v dd 5.0 10 ma i oz 3-state output leakage current v oh = v ss or v dd ? -10 10 a i osh output short circuit current high 3.3v high drive (ob33p) 3.3v low drive (ob33l) 2.5v high drive (ob25h) 2.5v low drive (ob25l) v in = v ss v in = v ss v in = v ss v in = v ss 200 100 20 10 ma notes: 1. all process conditions. junction temperature: ? 40 to +110 c. 2. no pull-up resistor.
advanced v0.6 25 proasic plus family flash fpgas i osl output short circuit current low 3.3v high drive 3.3v low drive 2.5v high drive 2.5v low drive v in = v dd v in = v dd v in = v dd v in = v dd 2 00 100 2 00 100 ma c i/o i/o pad capacitance 10 pf c clk clock input pad capacitance 10 pf dc specifications (3.3v pci operation) symbol parameter condition min. max. units v dd supply voltage for core 2.3 2.7 v v ddp supply voltage for i/o ring 3.0 3.6 v v ih input high voltage 0.5v dpp v dpp + 0.5 v v il input low voltage ? 0.5 0.3v ddp v i ipu input pull-up voltage 1 0.7v ddp v i il input leakage current 2 0 < v in < v cci ? 10 +10 a v oh output high voltage i out = ? 500 ? 0.9v dpp v v ol output low voltage i out = 1500 ? 0.1v dpp v c in input pin capacitance 3 10 pf c clk clk pin capacitance 5 12 pf notes: 1. this specification is guaranteed by design. it is the minimum voltage to which pull-up resistors are calculated to pull a flo ated network. applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this in put voltage. 2. input leakage currents include hi-z output leakage for all bidirectional buffers with tristate outputs. 3. absolute maximum pin capacitance for a pci input is 10 pf (except for clk). dc electrical specifications (v ddp = 3.3v +/-0.3v and v dd 2.5+/-0.2v) (continued) symbol parameter conditions min. typ. max. units notes: 1. all process conditions. junction temperature: ? 40 to +110 c. 2. no pull-up resistor.
proasic plus family flash fpgas 26 advanced v0.6 ac specifications (3.3v pci revision 2.2 operation) symbol parameter condition min. max. units i oh(ac) switching current high 0 < v out 0.3v cci * ? 12v cci ma 0.3v cci v out < 0.9v cci *( ? 17.1 + (v ddp ? v out )) ma 0.7v cci < v out < v cci * (test point) vout = 0.7vcc * ? 32v cci ma i ol(ac) switching current low v cci > v out 0.6v cci *16v ddp ma 0.6v cci > v out > 0.1v cci 1(26.7v out )ma 0.18v cci > v out > 0 * see page 21, equa- tion b of pci rev. 2.2 spec (test point) v out = 0.18v cc * 38v cci ma i cl low clamp current ? 3 < v in ? 1 ? 25 + (v in + 1)/0.015 ma i ch high clamp current v cci + 4 > v in v cci + 1 25 + (v in ? v ddp ? 1)/0.015 ma slew r output rise slew rate 0.2v cci to 0.6v cci load * 1 4 v/ns slew f output fall slew rate 0.6v cci to 0.2v cci load * 1 4 v/ns note: * refer to the pci specification document rev. 2.2. output buffer 1/2 in. max. 10 pf 1k ? pin 1k ? pin buffer output 10 pf
advanced v0.6 27 proasic plus family flash fpgas timing control and characteristics clock conditioning circuit proasic plus devices provide designers with very flexible clocking capabilities. each side of the chip contains a clock conditioning circuit based upon a 240 mhz phase-locked loop (pll) block ( figure 19 on page 28 ). two global multiplexed lines extend along each side of the chip to provide bidirectional access to the pll on that side (neither mux can be connected to the opposite side ? s pll). each global line has optional pecl input pads (described below). the global lines may be driven by either the pecl global input pad or the outputs from the pll block or both. each can be driven by a different output from the pll. the 2 signals available to drive the global networks are as follows: global a: output from global mux a conditioned version of pll output (f out ) ? delayed or advanced ? 0 , 90 , 180 , and 270 phase shift (with optional time advance) divided version of either of the above delayed version of either of the above (0.25ns, 0.50ns, or 4.00ns delay). 3 global b: output from global mux b delayed or advanced version of f out divided version of either of the above delayed version of either of the above (0.25ns, 0.50ns, or 4.00ns delay). 3 each pll block contains four programmable dividers as shown in figure 20 on page 28 . the first ( n ) provides all integer divisors from 1 to 16. the second and third ( u and v ) permit the signal applied to the global network to be further divided by factors of 2, 3 or 4. the fourth divider ( m , located in the direct feedback path) is controlled by 6 bits, allowing the incoming clock signal to be multiplied by integer factors from 1 to 64. the implementations m/(n*u) and m/(n*v) enable the user to define a wide range of multipliers and divisors factors. the clock conditioning circuit can advance or delay the clock up to 4ns (in increments of 0.25ns) relative to the positive edge of the incoming reference clock. the system also allows for the selection of output frequency clock phases of 0 , 90 , 180 , and 270 . a ? lock ? signal is provided to indicate that the pll has locked to the incoming signal, and a ? standby ? signal switches the pll block off when it is not locked to a signal. that allows pre-selected signals to be passed directly through, at least to the corresponding rib drivers. prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. these units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. not all possible combinations of input and output mode can be used. the degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted. this avoids unnecessary and unwieldy design kit and software work. the pll can be configured internally during design (via flash-configuration bits set in the programming bitstream) or externally during operation. this is done through a simple, dynamically accessible asynchronous interface ? a dedicated register file, which allows user signals to initiate parameter changes, such as pll divide/multiply ratios. for information on the clock conditioning circuit, refer to the, u sing proasic plus clock conditioning circuits application note. 3. this mode is available through the delay feature of the global mux driver.
proasic plus family flash fpgas 28 advanced v0.6 figure 19 pll block ? top-level view figure 20 pll block ? detailed block diagram external feedback signal avdd agnd vdd gnd output a output b to/from mask programmable delay dynamic configuration bits flash configuration bits 84 24 dynamic configuration bit inputs stand-by mode of core data in shift clock shift enable update nvm/register mode (other three bits used for flash configuration) dynamic configuration bit outputs lock detect data out gnd ( spare 1) gnd (spare 2) pll block + - clock from core lvpecl global mux a out global mux b out n m u v d d d d pll core external feedback global mux a out global mux b out output a output b 0? 90? 180? 270?
advanced v0.6 29 proasic plus family flash fpgas logic tile timing characteristics timing characteristics for proasic plus devices fall into three categories: family dependent, device dependent, and design dependent. the input and output buffer characteristics are common to all proasic plus family members. internal routing delays are device dependent. design dependency means that actual delays are not determined until after placement and routing of the user ? s design are complete. delay values may then be determined by using the timer utility or performing simulation with post-layout delays. critical nets and typical nets propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. critical net delays can then be applied to the most timing critical paths. critical nets are determined by net property assignment prior to placement and routing. up to 6 percent of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. refer to the actel designer user ? s guide for details on using constraints. high speed very long lines some nets in the design are very long lines, which are special routing resources that span multiple rows, columns or modules. this increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. typically, up to 6 percent of nets in a fully utilized device require very long lines. very long lines contribute from 4ns to 8.4ns routing delay. this additional delay is represented statistically in higher fanout routing delays. timing derating since proasic plus devices are manufactured with a cmos process, device performance will vary with temperature, voltage, and process. minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications).
proasic plus family flash fpgas 30 advanced v0.6 tristate buffer delays tristate buffer delays (worst-case commercial conditions, v ddp = 3.0v, v dd = 2.3v, 35 pf load, t j = 70c) macro type description max t dlh max t dhl max t enzh max t enzl units otb33ph 3.3v, pci output current, high slew rate 2.4 2.2 4.4 3.7 ns otb33pn 3.3v, pci output current, nominal slew rate 2.9 2.7 5.0 5.5 ns otb33pl 3.3v, pci output current, low slew rate 3.5 3.4 5.5 6.9 ns otb33lh 3.3v, low output current, high slew rate 3.4 3.8 6.2 6.1 ns otb33ln 3.3v, low output current, nominal slew rate 4.3 4.5 7.0 9.3 ns otb33ll 3.3v, low output current, low slew rate 4.9 6.3 7.8 12.3 ns otb25hh 2.5v, high output current, high slew rate 2.7 2.2 7.2 3.5 ns otb25hn 2.5v, high output current, nominal slew rate 3.5 3.2 7.5 5.1 ns otb25hl 2.5v, high output current, low slew rate 4.2 3.6 8.5 6.4 ns otb25lh 2.5v, low output current, high slew rate 3.9 4.9 10.8 5.4 ns otb25ln 2.5v, low output current, nominal slew rate 5.7 4.6 11.5 8.4 ns otb25ll 2.5v, low output current, low slew rate 7.1 6.0 12.4 11.1 ns otb25lphh 2.5v, low power, high output current, high slew rate 6.0 1.9 5.3 4.6 ns otb25lphn 2.5v, low power, high output current, nominal slew rate 5.9 2.8 6.2 7.7 ns otb25lphl 2.5v, low power, high output current, low slew rate 5.9 4.3 7.1 9.7 ns otb25lplh 2.5v, low power, low output current, high slew rate 9.2 2.7 7.7 8.1 ns otb25lpln 2.5v, low power, low output current, nominal slew rate 9.2 3.8 8.9 12.8 ns otb25lpll 2.5v, low power, low output current, low slew rate 9.2 5.4 10.2 17.4 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low 3. t enzh = enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low pad a otbx a 50% pa d v ol v oh 50% t dlh 50% 50% t dhl en 50% pa d v ol 50% t enzl 50% 10% en 50% pad gnd v oh 50% t enzh 50% 90% v cc en
advanced v0.6 31 proasic plus family flash fpgas output buffer delays output buffer delays pad a obx a 50% pad v ol v oh 50% t dlh 50% 50% t dhl (worst-case commercial conditions, v ddp = 3.0v, v dd = 2.3v, 35 pf load, t j = 70 c) macro type description max t dlh max t dhl max t enzh max t enzl units otb33ph 3.3v, pci output current, high slew rate 2.4 2.2 2.6 2.7 ns otb33pn 3.3v, pci output current, nominal slew rate 2.9 2.7 3.1 3.3 ns otb33pl 3.3v, pci output current, low slew rate 3.5 3.4 3.7 3.9 ns otb33lh 3.3v, low output current, high slew rate 3.4 3.8 3.6 4.3 ns otb33ln 3.3v, low output current, nominal slew rate 4.3 4.5 4.5 5.1 ns otb33ll 3.3v, low output current, low slew rate 4.9 6.3 5.1 6.8 ns otb25hh 2.5v, high output current, high slew rate 2.7 2.2 2.9 2.8 ns otb25hn 2.5v, high output current, nominal slew rate 3.5 3.2 3.7 3.8 ns otb25hl 2.5v, high output current, low slew rate 4.2 3.6 4.4 4.1 ns otb25lh 2.5v, low output current, high slew rate 3.9 4.9 4.1 5.4 ns otb25ln 2.5v, low output current, nominal slew rate 5.7 4.6 5.9 5.2 ns otb25ll 2.5v, low output current, low slew rate 7.1 6.0 7.4 6.5 ns otb25lphh 2.5v, low power, high output current, high slew rate 6.0 1.9 6.2 2.4 ns otb25lphn 2.5v, low power, high output current, nominal slew rate 5.9 2.8 6.1 3.4 ns otb25lphl 2.5v, low power, high output current, low slew rate 5.9 4.3 6.1 4.9 ns otb25lplh 2.5v, low power, low output current, high slew rate 9.2 2.7 9.4 3.2 ns otb25lpln 2.5v, low power, low output current, nominal slew rate 9.2 3.8 9.4 4.3 ns otb25lpll 2.5v, low power, low output current, low slew rate 9.2 5.4 9.4 5.9 ns notes: 1. t dlh = data-to-pad high 2. t dhl = data-to-pad low 3. t enzh = enable-to-pad, z to high 4. t enzl = enable-to-pad, z to low
proasic plus family flash fpgas 32 advanced v0.6 input buffer delays input buffer delays global input buffer delays predicted global routing delay* global routing skew (worst-case commercial conditions, v ddp = 3.0v, v dd = 2.3v, t j = 70 c, f clock = 250 mhz) macro type description max. t inyh max. t inyl units ib25 2.5v, cmos input levels, no pull-up resistor 0.5 0.8 ns ib25 2.5v, cmos input levels, no pull-up resistor 0.8 0.8 ns ib25lp 2.5v, cmos input levels, low power 1.1 0.7 ns ib25lps 2.5v, cmos input levels, low power 0.9 0.9 ns ib33 3.3v, cmos input levels, no pull-up resistor 0.9 0.6 ns ib33s 3.3v, cmos input levels, no pull-up resistor 1.2 0.5 ns notes: 1. t inyh = input pad-to-y high 2. t inyl = input pad-to-y low (worst-case commercial conditions, v ddp = 3.0v, v dd = 2.3v, t j = 70 , f clock = 250 mhz) macro type description max. t inyh max. t inyl units gl25 2.5v, cmos input levels 1.9 1.6 ns gl25s 2.5v, cmos input levels 1.8 1.8 ns gl25lp 2.5v, cmos input levels 1.7 2.2 ns gl25lps 2.5v, cmos input levels 1.9 1.9 ns gl33 3.3v, cmos input levels 1.9 1.6 ns gl33s 3.3v, cmos input levels 2.2 1.5 ns (worst-case commercial conditions, v ddp = 3.0v, v dd = 2.3v, t j = 70 c, f clock = 250 mhz) parameter description max. units t rckh input low to high (fully loaded row 32 inputs) 1.2 ns t rckl input high to low (fully loaded row 32 inputs) 1.1 ns t rckh input low to high (minimally loaded row 1 input) 0.9 ns t rckl input high to low (minimally loaded row 1 input) 0.9 ns * the timing delay difference between tile locations is less than 15ps. pad y pad v cc 0v 50% y gnd v cc 50% t inyh 50% 50% t inyl ibx (worst-case commercial conditions, v ddp = 3.0v, v dd = 2.3v, t j = 70 c, f clock = 250 mhz) parameter description max. units t rckswh maximum skew low to high 0.3 ns t rckshh maximum skew high to low 0.3 ns
advanced v0.6 33 proasic plus family flash fpgas module delays sample macrocell library listing (worst-case commercial conditions, v dd = 2.3v, t j = 70 o c) cell name description maximum intrinsic delay minimum setup/hold units nand2 2-input nand 0.4 ns and2 2-input and 0.4 ns nor3 3-input nor 0.4 ns mux2l 2-1 mux with active low select 0.4 ns oa21 2-input or into a 2-input and 0.4 ns xor2 2-input exclusive or 0.3 ns ldl active low latch (lh/hl) d: 0.3/0.2 t setup 0.5 t hold 0.2 ns dffl negative edge-triggered d-type flip-flop (lh/hl) clk-q: 0.4/0.4 t setup 0.4 t hold 0.2 ns note: assumes fanout of two. a b c y a b 50% y 50% 50% 50% 50% 50% t dalh c 50% 50% 50% 50% 50% t dblh t dahl t dbhl t dchl t dclh 50%
proasic plus family flash fpgas 34 advanced v0.6 slew rates measured at c = 10pf, nominal power supplies and 25 c type trig. lev. rising edge slew rate falling edge slew rate ps v/ns ps v/ns ob33ph 20%-60% 397 3.33 390 -3.38 ob33pn 20%-60% 463 2.85 450 -2.93 ob33pl 20%-60% 567 2.33 527 -2.51 ob33lh 20%-60% 467 2.83 700 -1.89 ob33ln 20%-60% 620 2.13 767 -1.72 ob33ll 20%-60% 813 1.62 1100 -1.20 ob25hh 20%-60% 750 1.33 310 -3.23 ob25hn 20%-60% 850 1.18 390 -2.56 ob25hl 20%-60% 1310 0.76 510 -1.96 ob25lh 20%-60% 793 1.26 430 -2.33 ob25ln 20%-60% 870 1.15 730 -1.37 ob25ll 20%-60% 1287 0.78 1037 -0.96 ob25lphh 20%-60% 470 2.13 433 -2.31 ob25lphn 20%-60% 533 1.81 527 -1.90 ob25lphl 20%-60% 770 1.30 753 -1.33 ob25lplh 20%-60% 597 1.68 707 -1.42 ob25lpln 20%-60% 873 1.15 760 -1.32 ob25lpll 20%-60% 1153 0.87 1563 -0.54
advanced v0.6 35 proasic plus family flash fpgas embedded memory specifications this section discusses proasic plus sram/fifo embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks ( table 4 ). table 3 on page 14 shows basic ram and fifo configurations. simultaneous read and write to the same location must be done with care. on such accesses the di bus is output to the do bus. enclosed timing diagrams?sram mode: synchronous ram read, access timed output strobe (synchronous transparent) synchronous ram read, pipeline mode outputs (synchronous pipelined) asynchronous ram write asynchronous ram read, address controlled, rdb=0 asynchronous ram read, rdb controlled synchronous ram write embedded memory specifications note: the difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. in transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. if clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). processing of this data in the same clock cycle is thus nearly impossible. most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. an entire clock cycle can then be used to process the data. to simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. in this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. table 4 memory block sram interface signals sram signal bits in/out description wclks 1 in write clock used on synchronization on write side rclks 1 in read clock used on synchronization on read side raddr<0:7> 8 in read address rblkb 1 in negative true read block select rdb 1 in negative true read pulse waddr<0:7> 8 in write address wblkb 1 in negative true write block select di<0:8> 9 in input data bits <0:8>, <8> can be used for parity in wrb 1 in negative true write pulse do<0:8> 9 out output data bits <0:8>, <8> can be used for parity out rpe 1 out read parity error wpe 1 out write parity error parodd 1 in selects odd parity generation/detect when high, even when low note: not all signals shown are used in all modes.
proasic plus family flash fpgas 36 advanced v0.6 synchronous ram read, access timed output strobe (synchronous transparent) note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns oca new do access from rclks 7.5 ns och old do valid from rclks 3.0 ns rach raddr hold from rclks 0.5 ns racs raddr setup to rclks 1.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 9.5 ns rpch old rpe valid from rclks 3.0 ns raddr rpe do rclks rbd, rblkb new valid data out cycle start old data out new valid address t racs t rdcs t rdch t rach t och t rpch t cmh t oca t rpca t ccyc t cml
advanced v0.6 37 proasic plus family flash fpgas synchronous ram read, pipeline mode outputs (synchronous pipelined) note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns oca new do access from rclks 2.0 ns och old do valid from rclks 0.75 ns rach raddr hold from rclks 0.5 ns racs raddr setup to rclks 1.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 4.0 ns rpch old rpe valid from rclks 1.0 ns rclks rpe do new valid data out cycle start new rpe out raddr new valid address rdb, rblkb t racs t oca t rpch t och t rpca t cml t cmh t ccyc t rach t rdch t rdcs old data out old rpe out
proasic plus family flash fpgas 38 advanced v0.6 asynchronous ram write note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes awrh waddr hold from wb 1.0 ns awrs waddr setup to wb 0.5 ns dwrh di hold from wb 1.5 ns dwrs di setup to wb 0.5 ns pargen is inactive dwrs di setup to wb 2.5 ns pargen is active wpda wpe access from di 3.0 ns wpe is invalid while pargen is active wpdh wpe hold from di 1.0 ns wrcyc cycle time 7.5 ns wrmh wb high phase 3.0 ns inactive wrml wb low phase 3.0 ns active wrb, wblkb waddr wpe di t awrs t wpda t awrh t dwrs t wrml t wrmh t wrcyc t wpdh t dwrh
advanced v0.6 39 proasic plus family flash fpgas asynchronous ram read, address controlled, rdb=0 note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes acyc read cycle time 7.5 ns oaa new do access from raddr stable 7.5 ns oah old do hold from raddr stable 3.0 ns rpaa new rpe access from raddr stable 10.0 ns rpah old rpe hold from raddr stable 3.0 ns rpe do raddr t oah t rpah t oaa t rpaa t acyc
proasic plus family flash fpgas 40 advanced v0.6 asynchronous ram read, rdb controlled note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns rdcyc read cycle time 7.5 ns rdmh rb high phase 3.0 ns inactive setup to new cycle rdml rb low phase 3.0 ns active rprda new rpe access from rb 9.5 ns rprdh old rpe valid from rb 3.0 ns rb=(rdb+rblkb) rpe do t ordh t orda t rprda t rdml t rdcyc t rdmh t rprdh
advanced v0.6 41 proasic plus family flash fpgas synchronous ram write note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns dch di hold from wclks 0.5 ns dcs di setup to wclks 1.0 ns wach waddr hold from wclks 0.5 ns wdcs waddr setup to wclks 1.0 ns wpca new wpe access from wclks 3.0 ns wpe is invalid while pargen is active wpch old wpe valid from wclks 0.5 ns wrch, wbch wrb & wblkb hold from wclks 0.5 ns wrcs, wbcs wrb & wblkb setup to wclks 1.0 ns note: on simultaneous read and write accesses to the same location di is output to do. wclks wpe waddr, di wrb, wblkb cycle start t wrch , t wbch t wrcs , t wbcs t dcs , t wdcs t wpch t dch , t wach t wpca t cmh t cml t ccyc
proasic plus family flash fpgas 42 advanced v0.6 synchronous write and read to the same location note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns wclkrclks wclks to rclks setup time ? 0.1 ns wclkrclkh wclks to rclks hold time 7.0 ns och old do valid from rclks 3.0 ns oca/och displayed for access timed output oca new do valid from rclks 7.5 ns notes: 1. this behavior is valid for access timed output and pipelined mode output. the table shows the timings of an access timed outp ut. 2. during synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. the negative setup time insures this behavior for wclks a nd rclks driven by the same design signal. 3. if wclks changes after the hold time, the data will be read. 4. a setup or hold time violation will result in unknown output data. * new data is read if wclks occurs before setup time. the data stored is read if wclks occurs after hold time. rclks do wclks t wclkrclkh new data* last cycle data t wclkrclks t och t oca
advanced v0.6 43 proasic plus family flash fpgas asynchronous write and synchronous read to the same location note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns wbrclks wb to rclks setup time ? 0.1 ns wbrclkh wb to rclks hold time 7.0 ns och old do valid from rclks 3.0 ns oca/och displayed for access timed output oca new do valid from rclks 7.5 ns dwrrclks di to rclks setup time 0 ns dwrh di to wb hold time 1.5 ns notes: 1. this behavior is valid for access timed output and pipelined mode output. the table shows the timings of an access timed outp ut. 2. in asynchronous write and synchronous read access to the same location, the new write data will be read out if the active wri te signal edge occurs before or at the same time as the active read clock edge. if wb changes to low after hold time, the data will be read. 3. a setup or hold time violation will result in unknown output data. * new data is read if wb occurs before setup time. the stored data is read if wb occurs after hold time. wb = {wrb + wblkb} rclks do t wclkrclkh new data* last cycle data t wclkrclks t och t oca di t dwrrclks t dwrh
proasic plus family flash fpgas 44 advanced v0.6 asynchronous write and read to the same location note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns owra new do access from wb 3.0 ns owrh old do valid from wb 0.5 ns rawrs rb or raddr from wb 5.0 ns rawrh rb or raddr from wb 5.0 ns notes: 1. during an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. violation or rawrs will disturb access to the old data. 3. violation of rawrh will disturb access to the newer data. rb, raddr old newer new t orda t ordh t owrh t rawrh wb = {wrb+wblkb} do t owra t rawrs
advanced v0.6 45 proasic plus family flash fpgas synchronous write and asynchronous read to the same location note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns owra new do access from wclks 3.0 ns owrh old do valid from wclks 0.5 ns rawclks rb or raddr from wclks 5.0 ns rawclkh rb or raddr from wclks 5.0 ns notes: 1. during an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. violation of rawclks will disturb access to old data. 3. violation of rawclkh will disturb access to newer data. rb, raddr old new newer t orda t ordh t rawclks t rawclkh wclks do t owrh t owra
proasic plus family flash fpgas 46 advanced v0.6 asynchronous fifo full and empty transitions the asynchronous fifo accepts writes and reads while not full or not empty. when the fifo is full, all writes are inhibited. conversely, when the fifo is empty, all reads are inhibited. a problem is created if the fifo is written during the transition out of full to not full or read during the transition out of empty to not empty. the exact time at which the write (read) operation changes from inhibited to accepted after the read (write) signal which causes the transition from full (empty) to not full (empty) is indeterminate. this indeterminate period starts 1 ns after the rb (wb) transition, which deactivates full (not empty) and ends 3 ns after the rb (wb) transition for slow cycles. for fast cycles, the indeterminate period ends 3 ns (7.5 ns ? rdl (wrl)) after the rb (wb) transition, whichever is later ( table 5 ). the timing diagram for write is shown in figure 21 on page 47 . the timing diagram for read is shown in figure 22 on page 47 . for basic ram configurations, see table 3 on page 14 . enclosed timing diagrams ? fifo mode: asynchronous fifo read asynchronous fifo write synchronous fifo read, access timed output strobe (synchronous transparent) synchronous fifo read, pipeline mode outputs (synchronous pipelined) synchronous fifo write fifo reset table 5 memory block fifo interface signals fifo signal bits in/out description wclks 1 in write clock used for synchronization on write side rclks 1 in read clock used for synchronization on read side level <0:7> 8 in direct configuration implements static flag logic rblkb 1 in negative true read block select rdb 1 in negative true read pulse reset 1 in negative true reset for fifo pointers wblkb 1 in negative true write block select di<0:8> 9 in input data bits <0:8>, <8> will be generated if pargen is true wrb 1 in negative true write pulse full, empty 2 out fifo flags. full prevents write and empty prevents read eqth, geqth 2 out eqth is true when the fifo holds the number of words specified by the level signal. geqth is true when the fifo holds (level) words or more do<0:8> 9 out output data bits <0:8> rpe 1 out read parity error wpe 1 out write parity error lgdep <0:2> 3 in configures depth of the fifo to 2 (lgdep+1) parodd 1 in selects odd parity generation/detect when high, even when low
advanced v0.6 47 proasic plus family flash fpgas figure 21 write timing diagram figure 22 read timing diagram write accepted write inhibited full rb write cycle 1ns 3ns wb read accepted read inhibited empty wb read cycle 1ns 3ns rb
proasic plus family flash fpgas 48 advanced v0.6 asynchronous fifo read t j = 0 c to 110 c; v dd = 2.3v to 2.7v note: the plot shows the normal operation status. symbol t xxx description min. max. units notes erdh, frdh, thrdh old empty, full, eqth, & geth valid hold time from rb 0.5 ns empty/full/thresh are invalid from the end of hold until the new access is complete erda new empty access from rb 3.0 1 ns frda full access from rb 3.0 1 ns orda new do access from rb 7.5 ns ordh old do valid from rb 3.0 ns rdcyc read cycle time 7.5 ns rdwrs wb , clearing empty, setup to rb 3.0 2 ns enabling the read operation 1.0 ns inhibiting the read operation rdh rb high phase 3.0 ns inactive rdl rb low phase 3.0 ns active rprda new rpe access from rb 9.5 ns rprdh old rpe valid from rb 4.0 ns thrda eqth or geth access from rb 4.5 ns notes: 1. at fast cycles, erda & frda = max (7.5 ns ? rdl), 3.0 ns 2. at fast cycles, rdwrs (for enabling read) = max (7.5 ns ? wrl), 3.0 ns rb=(rdb+rblkb) rpe rdata empty eqth, geth full (empty inhibits read) cycle start wb t rdwrs t erdh , t frdh t erda , t frda t thrdh t ordh t rprdh t orda t thrda
advanced v0.6 49 proasic plus family flash fpgas asynchronous fifo write t j = 0 c to 110 c; v dd = 2.3v to 2.7v note: the plot shows the normal operation status. symbol t xxx description min. max. units notes dwrh di hold from wb 1.5 ns dwrs di setup to wb 0.5 ns pargen is inactive dwrs di setup to wb 2.5 ns pargen is active ewrh, fwrh, thwrh old empty, full, eqth, & geth valid hold time after wb 0.5 ns empty/full/thresh are invalid from the end of hold until the new access is complete ewra empty access from wb 3.0 1 ns fwra new full access from wb 3.0 1 ns thwra eqth or geth access from wb 4.5 ns wpda wpe access from di 3.0 ns wpe is invalid while pargen is active wpdh wpe hold from di 1.0 ns wrcyc cycle time 7.5 ns wrrds rb , clearing full, setup to wb 3.0 2 ns enabling the write operation 1.0 inhibiting the write operation wrh wb high phase 3.0 ns inactive wrl wb low phase 3.0 ns active notes: 1. at fast cycles, ewra, fwra = max (7.5 ns ? wrl), 3.0 ns 2. at fast cycles, wrrds (for enabling write) = max (7.5 ns ? rdl), 3.0 ns wpe wdata (full inhibits write) wb=(wrb+wblkb) empty eqth, geth full cycle start rb t wrrds t dwrh t wpdh t wpda t dwrs t ewrh , t fwrh t ewra , t fwra t thwrh t thwra t wrh t wrl t wrcyc
proasic plus family flash fpgas 50 advanced v0.6 synchronous fifo read, access timed output strobe (synchronous transparent) t j = 0 c to 110 c; v dd = 2.3v to 2.7v note: the plot shows the normal operation status. symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns ecba new empty access from rclks 3.0 1 ns fcba full access from rclks 3.0 1 ns ecbh, fcbh, thcbh old empty, full, eqth, & geth valid hold time from rclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete oca new do access from rclks 7.5 ns och old do valid from rclks 3.0 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 9.5 ns rpch old rpe valid from rclks 3.0 ns hcba eqth or geth access from rclks 4.5 ns note: 1. at fast cycles, ecba & fcba = max (7.5 ns ? cmh), 3.0 ns rclk rpe rdata empty eqth, geth full old data out new valid data out (empty inhibits read) rdb cycle start t rdch t och t rpch t rdcs t ecbh , t fcbh t ecba , t fcba t oca t rpca t cmh t cml t ccyc t thcbh t hcba
advanced v0.6 51 proasic plus family flash fpgas synchronous fifo read, pipeline mode outputs (synchronous pipelined) t j = 0 c to 110 c; v dd = 2.3v to 2.7v note: the plot shows the normal operation status. symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns ecba new empty access from rclks 3.0 1 ns fcba full access from rclks 3.0 1 ns ecbh, fcbh, thcbh old empty, full, eqth, & geth valid hold time from rclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete oca new do access from rclks 2.0 ns och old do valid from rclks 0.75 ns rdch rdb hold from rclks 0.5 ns rdcs rdb setup to rclks 1.0 ns rpca new rpe access from rclks 4.0 ns rpch old rpe valid from rclks 1.0 ns hcba eqth or geth access from rclks 4.5 ns note: 1. at fast cycles, ecba & fcba = max (7.5 ns ? cms), 3.0 ns rclk rpe rdata empty eqth, geth full old data out new valid data out rdb cycle start old rpe out new rpe out t ecbh , t fcbh t rdch t rdcs t oca t ecba , t fcba t thcbh t hcba t cmh t cml t ccyc t rpch t och t rpca
proasic plus family flash fpgas 52 advanced v0.6 synchronous fifo write note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes ccyc cycle time 7.5 ns cmh clock high phase 3.0 ns cml clock low phase 3.0 ns dch di hold from wclks 0.5 ns dcs di setup to wclks 1.0 ns fcba new full access from wclks 3.0 1 ns ecba empty access from wclks 3.0 1 ns ecbh, fcbh, thcbh old empty, full, eqth, & geth valid hold time from wclks 1.0 ns empty/full/thresh are invalid from the end of hold until the new access is complete hcba eqth or geth access from wclks 4.5 ns wpca new wpe access from wclks 3.0 ns wpe is invalid while pargen is active wpch old wpe valid from wclks 0.5 ns wrch, wbch wrb & wblkb hold from wclks 0.5 ns wrcs, wbcs wrb & wblkb setup to wclks 1.0 ns note: 1. at fast cycles, ecba & fcba = max (7.5 ns ? cmh), 3.0 ns wclks wpe di empty eqth, geth full (full inhibits write) wrb, wblkb cycle start t wrch , t wbch t ecbh , t fcbh t ecba , t fcba t hcba t wrcs , t wbcs t dcs t wpca t cmh t cml t ccyc t wpch t dch t hcbh
advanced v0.6 53 proasic plus family flash fpgas fifo reset note: the plot shows the normal operation status. t j = 0 c to 110 c; v dd = 2.3v to 2.7v symbol t xxx description min. max. units notes cbrsh wclks or rclks hold from resetb 1.5 ns synchronous mode only cbrss wclks or rclks setup to resetb 1.5 ns synchronous mode only ersa new empty access from resetb 3.0 ns frsa full access from resetb 3.0 ns rsl resetb low phase 7.5 ns thrsa eqth or geth access from resetb 4.5 ns wbrsh wb hold from resetb 1.5 ns asynchronous mode only wbrss wb setup to resetb 1.5 ns asynchronous mode only *wb = wrb + wblrb resetb empty eqth, geth full wb* cycle start cycle start wclks, rclks t ersa , t frsa t thrsa t cbrss t wbrss t cbrsh t wbrsh t rsl
proasic plus family flash fpgas 54 advanced v0.6 pin description i/o user input/output the i/o pin functions as an input, output, tristate, or bidirectional buffer. input and output signal levels are compatible with standard lvttl and lvcmos specifications. unused i/o pins are configured as inputs with pull-up resistors. nc no connect to maintain compatibility with other actel proasic products it is recommended that this pin not be connected to the circuitry on the board. gl global input pin low skew input pin for clock or other global signals. input only. this pin can be configured with a pull-up resistor. gnd ground common ground supply voltage. v dd logic array power supply pin 2.5v supply voltage. v ddp i/o pad power supply pin 2.5v or 3.3v supply voltage. v pp programming supply pin this pin may be connected to any voltage between gnd and 16.5v during normal operation, or it can be left unconnected. for information on using this pin during programming, see the performing internal in-system programming using actel ? s proasic plus devices application note . v pn programming supply pin this pin may be connected to any voltage between gnd and 13.8v during normal operation, or it can be left unconnected. for information on using this pin during programming, see the performing internal in-system programming using actel ? s proasic plus devices application note . tms test mode select the tms pin controls the use of boundary-scan circuitry. tck test clock clock input pin for boundary scan. tdi test data in serial input for boundary scan. tdo test data out serial output for boundary scan. trst test reset input asynchronous, active low input pin for resetting boundary-scan circuitry. rck running clock a free running clock is needed during programming if the programmer cannot guarantee that tck will be uninterrupted. npecl pecl negative input provides high speed clock or data signals to the pll block. if unused, leave the pin unconnected. ppecl pecl positive input provides high speed clock or data signals to the pll block. if unused, leave the pin unconnected. avdd pll power supply agnd pll power ground
advanced v0.6 55 proasic plus family flash fpgas package pin assignments 208-pin pqfp 208-pin pqfp 1 208
proasic plus family flash fpgas 56 advanced v0.6 208-pin pqfp pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function 1 gnd gnd gnd gnd gnd gnd 2 i/o i/o i/o i/o i/o i/o 3 i/o i/o i/o i/o i/o i/o 4 i/o i/o i/o i/o i/o i/o 5 i/o i/o i/o i/o i/o i/o 6 i/o i/o i/o i/o i/o i/o 7 i/o i/o i/o i/o i/o i/o 8 i/o i/o i/o i/o i/o i/o 9 i/o i/o i/o i/o i/o i/o 10 i/o i/o i/o i/o i/o i/o 11 i/o i/o i/o i/o i/o i/o 12 i/o i/o i/o i/o i/o i/o 13 i/o i/o i/o i/o i/o i/o 14 i/o i/o i/o i/o i/o i/o 15 i/o i/o i/o i/o i/o i/o 16 v dd v dd v dd v dd v dd v dd 17 gnd gnd gnd gnd gnd gnd 18 i/o i/o i/o i/o i/o i/o 19 i/o i/o i/o i/o i/o i/o 20 i/o i/o i/o i/o i/o i/o 21 i/o i/o i/o i/o i/o i/o 22 v ddp v ddp v ddp v ddp v ddp v ddp 23 i/o i/o i/o i/o i/o i/o 24 gl gl gl gl gl gl 25 agnd agnd agnd agnd agnd agnd 26 npecl npecl npecl npecl npecl npecl 27 avdd avdd avdd avdd avdd avdd 28 ppecl ppecl ppecl ppecl ppecl ppecl 29 gnd gnd gnd gnd gnd gnd 30 gl gl gl gl gl gl 31 i/o i/o i/o i/o i/o i/o 32 i/o i/o i/o i/o i/o i/o 33 i/o i/o i/o i/o i/o i/o 34 i/o i/o i/o i/o i/o i/o 35 i/o i/o i/o i/o i/o i/o 36 v dd v dd v dd v dd v dd v dd 37 i/o i/o i/o i/o i/o i/o 38 i/o i/o i/o i/o i/o i/o 39 i/o i/o i/o i/o i/o i/o
advanced v0.6 57 proasic plus family flash fpgas 40 v ddp v ddp v ddp v ddp v ddp v ddp 41 gnd gnd gnd gnd gnd gnd 42 i/o i/o i/o i/o i/o i/o 43 i/o i/o i/o i/o i/o i/o 44 i/o i/o i/o i/o i/o i/o 45 i/o i/o i/o i/o i/o i/o 46 i/o i/o i/o i/o i/o i/o 47 i/o i/o i/o i/o i/o i/o 48 i/o i/o i/o i/o i/o i/o 49 i/o i/o i/o i/o i/o i/o 50 i/o i/o i/o i/o i/o i/o 51 i/o i/o i/o i/o i/o i/o 52 gnd gnd gnd gnd gnd gnd 53 v ddp v ddp v ddp v ddp v ddp v ddp 54 i/o i/o i/o i/o i/o i/o 55 i/o i/o i/o i/o i/o i/o 56 i/o i/o i/o i/o i/o i/o 57 i/o i/o i/o i/o i/o i/o 58 i/o i/o i/o i/o i/o i/o 59 i/o i/o i/o i/o i/o i/o 60 i/o i/o i/o i/o i/o i/o 61 i/o i/o i/o i/o i/o i/o 62 i/o i/o i/o i/o i/o i/o 63 i/o i/o i/o i/o i/o i/o 64 i/o i/o i/o i/o i/o i/o 65 gnd gnd gnd gnd gnd gnd 66 i/o i/o i/o i/o i/o i/o 67 i/o i/o i/o i/o i/o i/o 68 i/o i/o i/o i/o i/o i/o 69 i/o i/o i/o i/o i/o i/o 70 i/o i/o i/o i/o i/o i/o 71 v dd v dd v dd v dd v dd v dd 72 v ddp v ddp v ddp v ddp v ddp v ddp 73 i/o i/o i/o i/o i/o i/o 74 i/o i/o i/o i/o i/o i/o 75 i/o i/o i/o i/o i/o i/o 76 i/o i/o i/o i/o i/o i/o 77 i/o i/o i/o i/o i/o i/o 78 i/o i/o i/o i/o i/o i/o 208-pin pqfp (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 58 advanced v0.6 79 i/o i/o i/o i/o i/o i/o 80 i/o i/o i/o i/o i/o i/o 81 gnd gnd gnd gnd gnd gnd 82 i/o i/o i/o i/o i/o i/o 83 i/o i/o i/o i/o i/o i/o 84 i/o i/o i/o i/o i/o i/o 85 i/o i/o i/o i/o i/o i/o 86 i/o i/o i/o i/o i/o i/o 87 i/o i/o i/o i/o i/o i/o 88 v dd v dd v dd v dd v dd v dd 89 v ddp v ddp v ddp v ddp v ddp v ddp 90 i/o i/o i/o i/o i/o i/o 91 i/o i/o i/o i/o i/o i/o 92 i/o i/o i/o i/o i/o i/o 93 i/o i/o i/o i/o i/o i/o 94 i/o i/o i/o i/o i/o i/o 95 i/o i/o i/o i/o i/o i/o 96 i/o i/o i/o i/o i/o i/o 97 gnd gnd gnd gnd gnd gnd 98 i/o i/o i/o i/o i/o i/o 99 i/o i/o i/o i/o i/o i/o 100 i/o i/o i/o i/o i/o i/o 101 tck tck tck tck tck tck 102 tdi tdi tdi tdi tdi tdi 103 tms tms tms tms tms tms 104 v ddp v ddp v ddp v ddp v ddp v ddp 105 gnd gnd gnd gnd gnd gnd 106 v pp v pp v pp v pp v pp v pp 107 v pn v pn v pn v pn v pn v pn 108 tdotdotdotdotdotdo 109 trst trst trst trst trst trst 110 rck rck rck rck rck rck 111 i/o i/o i/o i/o i/o i/o 112 i/o i/o i/o i/o i/o i/o 113 i/o i/o i/o i/o i/o i/o 114 i/o i/o i/o i/o i/o i/o 115 i/o i/o i/o i/o i/o i/o 116 i/o i/o i/o i/o i/o i/o 117 i/o i/o i/o i/o i/o i/o 208-pin pqfp (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 59 proasic plus family flash fpgas 118 i/o i/o i/o i/o i/o i/o 119 i/o i/o i/o i/o i/o i/o 120 i/o i/o i/o i/o i/o i/o 121 i/o i/o i/o i/o i/o i/o 122 gnd gnd gnd gnd gnd gnd 123 v ddp v ddp v ddp v ddp v ddp v ddp 124 i/o i/o i/o i/o i/o i/o 125 i/o i/o i/o i/o i/o i/o 126 v dd v dd v dd v dd v dd v dd 127 i/o i/o i/o i/o i/o i/o 128 gl gl gl gl gl gl 129 ppecl ppecl ppecl ppecl ppecl ppecl 130 gnd gnd gnd gnd gnd gnd 131 avdd avdd avdd avdd avdd avdd 132 npecl npecl npecl npecl npecl npecl 133 agnd agnd agnd agnd agnd agnd 134 gl gl gl gl gl gl 135 i/o i/o i/o i/o i/o i/o 136 i/o i/o i/o i/o i/o i/o 137 i/o i/o i/o i/o i/o i/o 138 v ddp v ddp v ddp v ddp v ddp v ddp 139 i/o i/o i/o i/o i/o i/o 140 i/o i/o i/o i/o i/o i/o 141 gnd gnd gnd gnd gnd gnd 142 v dd v dd v dd v dd v dd v dd 143 i/o i/o i/o i/o i/o i/o 144 i/o i/o i/o i/o i/o i/o 145 i/o i/o i/o i/o i/o i/o 146 i/o i/o i/o i/o i/o i/o 147 i/o i/o i/o i/o i/o i/o 148 i/o i/o i/o i/o i/o i/o 149 i/o i/o i/o i/o i/o i/o 150 i/o i/o i/o i/o i/o i/o 151 i/o i/o i/o i/o i/o i/o 152 i/o i/o i/o i/o i/o i/o 153 i/o i/o i/o i/o i/o i/o 154 i/o i/o i/o i/o i/o i/o 155 i/o i/o i/o i/o i/o i/o 156 gnd gnd gnd gnd gnd gnd 208-pin pqfp (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 60 advanced v0.6 157 v ddp v ddp v ddp v ddp v ddp v ddp 158 i/o i/o i/o i/o i/o i/o 159 i/o i/o i/o i/o i/o i/o 160 i/o i/o i/o i/o i/o i/o 161 i/o i/o i/o i/o i/o i/o 162 gnd gnd gnd gnd gnd gnd 163 i/o i/o i/o i/o i/o i/o 164 i/o i/o i/o i/o i/o i/o 165 i/o i/o i/o i/o i/o i/o 166 i/o i/o i/o i/o i/o i/o 167 i/o i/o i/o i/o i/o i/o 168 i/o i/o i/o i/o i/o i/o 169 i/o i/o i/o i/o i/o i/o 170 v ddp v ddp v ddp v ddp v ddp v ddp 171 v dd v dd v dd v dd v dd v dd 172 i/o i/o i/o i/o i/o i/o 173 i/o i/o i/o i/o i/o i/o 174 i/o i/o i/o i/o i/o i/o 175 i/o i/o i/o i/o i/o i/o 176 i/o i/o i/o i/o i/o i/o 177 i/o i/o i/o i/o i/o i/o 178 gnd gnd gnd gnd gnd gnd 179 i/o i/o i/o i/o i/o i/o 180 i/o i/o i/o i/o i/o i/o 181 i/o i/o i/o i/o i/o i/o 182 i/o i/o i/o i/o i/o i/o 183 i/o i/o i/o i/o i/o i/o 184 i/o i/o i/o i/o i/o i/o 185 i/o i/o i/o i/o i/o i/o 186 v ddp v ddp v ddp v ddp v ddp v ddp 187 v dd v dd v dd v dd v dd v dd 188 i/o i/o i/o i/o i/o i/o 189 i/o i/o i/o i/o i/o i/o 190 i/o i/o i/o i/o i/o i/o 191 i/o i/o i/o i/o i/o i/o 192 i/o i/o i/o i/o i/o i/o 193 i/o i/o i/o i/o i/o i/o 194 i/o i/o i/o i/o i/o i/o 195 gnd gnd gnd gnd gnd gnd 208-pin pqfp (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 61 proasic plus family flash fpgas 196 i/o i/o i/o i/o i/o i/o 197 i/o i/o i/o i/o i/o i/o 198 i/o i/o i/o i/o i/o i/o 199 i/o i/o i/o i/o i/o i/o 200 i/o i/o i/o i/o i/o i/o 201 i/o i/o i/o i/o i/o i/o 202 i/o i/o i/o i/o i/o i/o 203 i/o i/o i/o i/o i/o i/o 204 i/o i/o i/o i/o i/o i/o 205 i/o i/o i/o i/o i/o i/o 206 i/o i/o i/o i/o i/o i/o 207 i/o i/o i/o i/o i/o i/o 208 v ddp v ddp v ddp v ddp v ddp v ddp 208-pin pqfp (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 62 advanced v0.6 package pin assignments (continued) 456-pin pbga (bottom view) 1 2 3 5 6 7 8 9 10 11 15 14 13 12 16 17 18 19 20 21 22 23 4 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
advanced v0.6 63 proasic plus family flash fpgas 456-pin pbga pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function a1 v ddp v ddp v ddp v ddp v ddp v ddp a2 v ddp v ddp v ddp v ddp v ddp v ddp a3 nc nc i/o i/o i/o i/o a4 nc nc i/o i/o i/o i/o a5 nc nc i/o i/o i/o i/o a6 nc nc i/o i/o i/o i/o a7 nc nc i/o i/o i/o i/o a8 i/o i/o i/o i/o i/o i/o a9 i/o i/o i/o i/o i/o i/o a10 i/o i/o i/o i/o i/o i/o a11 i/o i/o i/o i/o i/o i/o a12 i/o i/o i/o i/o i/o i/o a13 i/o i/o i/o i/o i/o i/o a14 i/o i/o i/o i/o i/o i/o a15 i/o i/o i/o i/o i/o i/o a16 i/o i/o i/o i/o i/o i/o a17 i/o i/o i/o i/o i/o i/o a18 i/o i/o i/o i/o i/o i/o a19 i/o i/o i/o i/o i/o i/o a20 nc nc i/o i/o i/o i/o a21 nc nc i/o i/o i/o i/o a22 nc nc i/o i/o i/o i/o a23 nc nc i/o i/o i/o i/o a24 nc nc i/o i/o i/o i/o a25 v ddp v ddp v ddp v ddp v ddp v ddp a26 v ddp v ddp v ddp v ddp v ddp v ddp b1 v ddp v ddp v ddp v ddp v ddp v ddp b2 v ddp v ddp v ddp v ddp v ddp v ddp b3 nc nc nc i/o i/o i/o b4 nc nc i/o i/o i/o i/o b5 nc nc i/o i/o i/o i/o b6 nc nc i/o i/o i/o i/o b7 nc nc i/o i/o i/o i/o b8 i/o i/o i/o i/o i/o i/o b9 i/o i/o i/o i/o i/o i/o b10 i/o i/o i/o i/o i/o i/o b11 i/o i/o i/o i/o i/o i/o b12 i/o i/o i/o i/o i/o i/o b13 i/o i/o i/o i/o i/o i/o
proasic plus family flash fpgas 64 advanced v0.6 b14 i/o i/o i/o i/o i/o i/o b15 i/o i/o i/o i/o i/o i/o b16 i/o i/o i/o i/o i/o i/o b17 i/o i/o i/o i/o i/o i/o b18 i/o i/o i/o i/o i/o i/o b19 i/o i/o i/o i/o i/o i/o b20 nc nc i/o i/o i/o i/o b21 nc nc i/o i/o i/o i/o b22 nc nc i/o i/o i/o i/o b23 nc nc i/o i/o i/o i/o b24 nc nc i/o i/o i/o i/o b25 v ddp v ddp v ddp v ddp v ddp v ddp b26 v ddp v ddp v ddp v ddp v ddp v ddp c1 v ddp v ddp v ddp v ddp v ddp v ddp c2 nc i/o i/o i/o i/o i/o c3 v ddp v ddp v ddp v ddp v ddp v ddp c4 nc nc nc i/o i/o i/o c5 nc nc i/o i/o i/o i/o c6 nc nc i/o i/o i/o i/o c7 i/o i/o i/o i/o i/o i/o c8 i/o i/o i/o i/o i/o i/o c9 i/o i/o i/o i/o i/o i/o c10 i/o i/o i/o i/o i/o i/o c11 i/o i/o i/o i/o i/o i/o c12 i/o i/o i/o i/o i/o i/o c13 i/o i/o i/o i/o i/o i/o c14 i/o i/o i/o i/o i/o i/o c15 i/o i/o i/o i/o i/o i/o c16 i/o i/o i/o i/o i/o i/o c17 i/o i/o i/o i/o i/o i/o c18 i/o i/o i/o i/o i/o i/o c19 i/o i/o i/o i/o i/o i/o c20 i/o i/o i/o i/o i/o i/o c21 nc nc i/o i/o i/o i/o c22 nc nc i/o i/o i/o i/o c23 nc nc i/o i/o i/o i/o c24 v ddp v ddp v ddp v ddp v ddp v ddp c25 nc nc nc i/o i/o i/o c26 nc nc nc i/o i/o i/o 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 65 proasic plus family flash fpgas d1 nc nc nc i/o i/o i/o d2 nc nc nc i/o i/o i/o d3 nc i/o i/o i/o i/o i/o d4 v ddp v ddp v ddp v ddp v ddp v ddp d5 nc nc i/o i/o i/o i/o d6 nc nc i/o i/o i/o i/o d7 i/o i/o i/o i/o i/o i/o d8 i/o i/o i/o i/o i/o i/o d9 i/o i/o i/o i/o i/o i/o d10 i/o i/o i/o i/o i/o i/o d11 i/o i/o i/o i/o i/o i/o d12 i/o i/o i/o i/o i/o i/o d13 i/o i/o i/o i/o i/o i/o d14 i/o i/o i/o i/o i/o i/o d15 i/o i/o i/o i/o i/o i/o d16 i/o i/o i/o i/o i/o i/o d17 i/o i/o i/o i/o i/o i/o d18 i/o i/o i/o i/o i/o i/o d19 i/o i/o i/o i/o i/o i/o d20 i/o i/o i/o i/o i/o i/o d21 i/o i/o i/o i/o i/o i/o d22 nc nc i/o i/o i/o i/o d23 v ddp v ddp v ddp v ddp v ddp v ddp d24 nc i/o i/o i/o i/o i/o d25 nc nc nc i/o i/o i/o d26 nc nc nc i/o i/o i/o e1 nc i/o i/o i/o i/o i/o e2 nc i/o i/o i/o i/o i/o e3 nc i/o i/o i/o i/o i/o e4 nc i/o i/o i/o i/o i/o e5 v dd v dd v dd v dd v dd v dd e6 v dd v dd v dd v dd v dd v dd e7 v dd v dd v dd v dd v dd v dd e8 v dd v dd v dd v dd v dd v dd e9 i/o i/o i/o i/o i/o i/o e10 i/o i/o i/o i/o i/o i/o e11 i/o i/o i/o i/o i/o i/o e12 i/o i/o i/o i/o i/o i/o e13 i/o i/o i/o i/o i/o i/o 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 66 advanced v0.6 e14 i/o i/o i/o i/o i/o i/o e15 i/o i/o i/o i/o i/o i/o e16 i/o i/o i/o i/o i/o i/o e17 i/o i/o i/o i/o i/o i/o e18 i/o i/o i/o i/o i/o i/o e19 i/o i/o i/o i/o i/o i/o e20 v dd v dd v dd v dd v dd v dd e21 v dd v dd v dd v dd v dd v dd e22 v dd v dd v dd v dd v dd v dd e23 nc i/o i/o i/o i/o i/o e24 nc i/o i/o i/o i/o i/o e25 nc i/o i/o i/o i/o i/o e26 nc i/o i/o i/o i/o i/o f1 nc i/o i/o i/o i/o i/o f2 nc i/o i/o i/o i/o i/o f3 nc i/o i/o i/o i/o i/o f4 nc i/o i/o i/o i/o i/o f5 v dd v dd v dd v dd v dd v dd f22 v dd v dd v dd v dd v dd v dd f23 nc i/o i/o i/o i/o i/o f24 nc i/o i/o i/o i/o i/o f25 nc i/o i/o i/o i/o i/o f26 nc i/o i/o i/o i/o i/o g1 i/o i/o i/o i/o i/o i/o g2 i/o i/o i/o i/o i/o i/o g3 nc i/o i/o i/o i/o i/o g4 nc i/o i/o i/o i/o i/o g5 v dd v dd v dd v dd v dd v dd g22 v dd v dd v dd v dd v dd v dd g23 nc i/o i/o i/o i/o i/o g24 nc i/o i/o i/o i/o i/o g25 nc i/o i/o i/o i/o i/o g26 i/o i/o i/o i/o i/o i/o h1 i/o i/o i/o i/o i/o i/o h2 i/o i/o i/o i/o i/o i/o h3 i/o i/o i/o i/o i/o i/o h4 i/o i/o i/o i/o i/o i/o h5 v dd v dd v dd v dd v dd v dd h22 v dd v dd v dd v dd v dd v dd 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 67 proasic plus family flash fpgas h23 i/o i/o i/o i/o i/o i/o h24 i/o i/o i/o i/o i/o i/o h25 i/o i/o i/o i/o i/o i/o h26 i/o i/o i/o i/o i/o i/o j1 i/o i/o i/o i/o i/o i/o j2 i/o i/o i/o i/o i/o i/o j3 i/o i/o i/o i/o i/o i/o j4 i/o i/o i/o i/o i/o i/o j5 i/o i/o i/o i/o i/o i/o j22 i/o i/o i/o i/o i/o i/o j23 i/o i/o i/o i/o i/o i/o j24 i/o i/o i/o i/o i/o i/o j25 i/o i/o i/o i/o i/o i/o j26 i/o i/o i/o i/o i/o i/o k1 i/o i/o i/o i/o i/o i/o k2 i/o i/o i/o i/o i/o i/o k3 i/o i/o i/o i/o i/o i/o k4 i/o i/o i/o i/o i/o i/o k5 i/o i/o i/o i/o i/o i/o k22 i/o i/o i/o i/o i/o i/o k23 i/o i/o i/o i/o i/o i/o k24 i/o i/o i/o i/o i/o i/o k25 i/o i/o i/o i/o i/o i/o k26 i/o i/o i/o i/o i/o i/o l1 i/o i/o i/o i/o i/o i/o l2 i/o i/o i/o i/o i/o i/o l3 i/o i/o i/o i/o i/o i/o l4 i/o i/o i/o i/o i/o i/o l5 i/o i/o i/o i/o i/o i/o l11 gnd gnd gnd gnd gnd gnd l12 gnd gnd gnd gnd gnd gnd l13 gnd gnd gnd gnd gnd gnd l14 gnd gnd gnd gnd gnd gnd l15 gnd gnd gnd gnd gnd gnd l16 gnd gnd gnd gnd gnd gnd l22 i/o i/o i/o i/o i/o i/o l23 i/o i/o i/o i/o i/o i/o l24 i/o i/o i/o i/o i/o i/o l25 i/o i/o i/o i/o i/o i/o 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 68 advanced v0.6 l26 i/o i/o i/o i/o i/o i/o m1 gl gl gl gl gl gl m2 gl gl gl gl gl gl m3 i/o i/o i/o i/o i/o i/o m4 i/o i/o i/o i/o i/o i/o m5 i/o i/o i/o i/o i/o i/o m11 gnd gnd gnd gnd gnd gnd m12 gnd gnd gnd gnd gnd gnd m13 gnd gnd gnd gnd gnd gnd m14 gnd gnd gnd gnd gnd gnd m15 gnd gnd gnd gnd gnd gnd m16 gnd gnd gnd gnd gnd gnd m22glglglglglgl m23 i/o i/o i/o i/o i/o i/o m24 i/o i/o i/o i/o i/o i/o m25 i/o i/o i/o i/o i/o i/o m26 i/o i/o i/o i/o i/o i/o n1 i/o i/o i/o i/o i/o i/o n2 i/o i/o i/o i/o i/o i/o n3 agnd agnd agnd agnd agnd agnd n4 ppecl ppecl ppecl ppecl ppecl ppecl n5 avdd avdd avdd avdd avdd avdd n11 gnd gnd gnd gnd gnd gnd n12 gnd gnd gnd gnd gnd gnd n13 gnd gnd gnd gnd gnd gnd n14 gnd gnd gnd gnd gnd gnd n15 gnd gnd gnd gnd gnd gnd n16 gnd gnd gnd gnd gnd gnd n22 npecl npecl npecl npecl npecl npecl n23glglglglglgl n24 avddavddavddavddavddavdd n25 i/o i/o i/o i/o i/o i/o n26 agnd agnd agnd agnd agnd agnd p1 i/o i/o i/o i/o i/o i/o p2 i/o i/o i/o i/o i/o i/o p3 i/o i/o i/o i/o i/o i/o p4 i/o i/o i/o i/o i/o i/o p5 npecl npecl npecl npecl npecl npecl p11 gnd gnd gnd gnd gnd gnd 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 69 proasic plus family flash fpgas p12 gnd gnd gnd gnd gnd gnd p13 gnd gnd gnd gnd gnd gnd p14 gnd gnd gnd gnd gnd gnd p15 gnd gnd gnd gnd gnd gnd p16 gnd gnd gnd gnd gnd gnd p22 i/o i/o i/o i/o i/o i/o p23 i/o i/o i/o i/o i/o i/o p24 i/o i/o i/o i/o i/o i/o p25 i/o i/o i/o i/o i/o i/o p26 ppecl ppecl ppecl ppecl ppecl ppecl r1 i/o i/o i/o i/o i/o i/o r2 i/o i/o i/o i/o i/o i/o r3 i/o i/o i/o i/o i/o i/o r4 i/o i/o i/o i/o i/o i/o r5 i/o i/o i/o i/o i/o i/o r11 gnd gnd gnd gnd gnd gnd r12 gnd gnd gnd gnd gnd gnd r13 gnd gnd gnd gnd gnd gnd r14 gnd gnd gnd gnd gnd gnd r15 gnd gnd gnd gnd gnd gnd r16 gnd gnd gnd gnd gnd gnd r22 i/o i/o i/o i/o i/o i/o r23 i/o i/o i/o i/o i/o i/o r24 i/o i/o i/o i/o i/o i/o r25 i/o i/o i/o i/o i/o i/o r26 i/o i/o i/o i/o i/o i/o t1 i/o i/o i/o i/o i/o i/o t2 i/o i/o i/o i/o i/o i/o t3 i/o i/o i/o i/o i/o i/o t4 i/o i/o i/o i/o i/o i/o t5 i/o i/o i/o i/o i/o i/o t11 gnd gnd gnd gnd gnd gnd t12 gnd gnd gnd gnd gnd gnd t13 gnd gnd gnd gnd gnd gnd t14 gnd gnd gnd gnd gnd gnd t15 gnd gnd gnd gnd gnd gnd t16 gnd gnd gnd gnd gnd gnd t22 i/o i/o i/o i/o i/o i/o t23 i/o i/o i/o i/o i/o i/o 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 70 advanced v0.6 t24 i/o i/o i/o i/o i/o i/o t25 i/o i/o i/o i/o i/o i/o t26 i/o i/o i/o i/o i/o i/o u1 i/o i/o i/o i/o i/o i/o u2 i/o i/o i/o i/o i/o i/o u3 i/o i/o i/o i/o i/o i/o u4 i/o i/o i/o i/o i/o i/o u5 i/o i/o i/o i/o i/o i/o u22 i/o i/o i/o i/o i/o i/o u23 i/o i/o i/o i/o i/o i/o u24 i/o i/o i/o i/o i/o i/o u25 i/o i/o i/o i/o i/o i/o u26 i/o i/o i/o i/o i/o i/o v1 i/o i/o i/o i/o i/o i/o v2 i/o i/o i/o i/o i/o i/o v3 i/o i/o i/o i/o i/o i/o v4 i/o i/o i/o i/o i/o i/o v5 i/o i/o i/o i/o i/o i/o v22 i/o i/o i/o i/o i/o i/o v23 i/o i/o i/o i/o i/o i/o v24 i/o i/o i/o i/o i/o i/o v25 i/o i/o i/o i/o i/o i/o v26 i/o i/o i/o i/o i/o i/o w1 i/o i/o i/o i/o i/o i/o w2 i/o i/o i/o i/o i/o i/o w3 i/o i/o i/o i/o i/o i/o w4 i/o i/o i/o i/o i/o i/o w5 v dd v dd v dd v dd v dd v dd w22 v dd v dd v dd v dd v dd v dd w23 i/o i/o i/o i/o i/o i/o w24 i/o i/o i/o i/o i/o i/o w25 i/o i/o i/o i/o i/o i/o w26 i/o i/o i/o i/o i/o i/o y1 i/o i/o i/o i/o i/o i/o y2 i/o i/o i/o i/o i/o i/o y3 i/o i/o i/o i/o i/o i/o y4 nc i/o i/o i/o i/o i/o y5 v dd v dd v dd v dd v dd v dd y22 v dd v dd v dd v dd v dd v dd 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 71 proasic plus family flash fpgas y23 nc i/o i/o i/o i/o i/o y24 nc i/o i/o i/o i/o i/o y25 nc i/o i/o i/o i/o i/o y26 nc i/o i/o i/o i/o i/o aa1 i/o i/o i/o i/o i/o i/o aa2 nc i/o i/o i/o i/o i/o aa3 nc i/o i/o i/o i/o i/o aa4 nc i/o i/o i/o i/o i/o aa5 v dd v dd v dd v dd v dd v dd aa22 v dd v dd v dd v dd v dd v dd aa23 nc i/o i/o i/o i/o i/o aa24 nc i/o i/o i/o i/o i/o aa25 nc i/o i/o i/o i/o i/o aa26 nc i/o i/o i/o i/o i/o ab1 nc i/o i/o i/o i/o i/o ab2 nc i/o i/o i/o i/o i/o ab3 nc i/o i/o i/o i/o i/o ab4 nc i/o i/o i/o i/o i/o ab5 v dd v dd v dd v dd v dd v dd ab6 v dd v dd v dd v dd v dd v dd ab7 v dd v dd v dd v dd v dd v dd ab8 i/o i/o i/o i/o i/o i/o ab9 i/o i/o i/o i/o i/o i/o ab10 i/o i/o i/o i/o i/o i/o ab11 i/o i/o i/o i/o i/o i/o ab12 i/o i/o i/o i/o i/o i/o ab13 i/o i/o i/o i/o i/o i/o ab14 i/o i/o i/o i/o i/o i/o ab15 i/o i/o i/o i/o i/o i/o ab16 i/o i/o i/o i/o i/o i/o ab17 i/o i/o i/o i/o i/o i/o ab18 i/o i/o i/o i/o i/o i/o ab19 i/o i/o i/o i/o i/o i/o ab20 v dd v dd v dd v dd v dd v dd ab21 v dd v dd v dd v dd v dd v dd ab22 v dd v dd v dd v dd v dd v dd ab23 nc i/o i/o i/o i/o i/o ab24 nc i/o i/o i/o i/o i/o ab25 nc i/o nc i/o i/o i/o 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 72 advanced v0.6 ab26 nc nc i/o i/o i/o i/o ac1 nc i/o i/o i/o i/o i/o ac2 nc i/o i/o i/o i/o i/o ac3 nc i/o i/o i/o i/o i/o ac4 v ddp v ddp v ddp v ddp v ddp v ddp ac5 nc nc i/o i/o i/o i/o ac6 i/o i/o i/o i/o i/o i/o ac7 i/o i/o i/o i/o i/o i/o ac8 i/o i/o i/o i/o i/o i/o ac9 i/o i/o i/o i/o i/o i/o ac10 i/o i/o i/o i/o i/o i/o ac11 i/o i/o i/o i/o i/o i/o ac12 i/o i/o i/o i/o i/o i/o ac13 i/o i/o i/o i/o i/o i/o ac14 i/o i/o i/o i/o i/o i/o ac15 i/o i/o i/o i/o i/o i/o ac16 i/o i/o i/o i/o i/o i/o ac17 i/o i/o i/o i/o i/o i/o ac18 i/o i/o i/o i/o i/o i/o ac19 i/o i/o i/o i/o i/o i/o ac20 i/o i/o i/o i/o i/o i/o ac21 tms tms tms tms tms tms ac22tdotdotdotdotdotdo ac23 v ddp v ddp v ddp v ddp v ddp v ddp ac24 rck rck rck rck rck rck ac25 nc nc i/o i/o i/o i/o ac26 nc i/o i/o i/o i/o i/o ad1 nc nc nc i/o i/o i/o ad2 nc i/o i/o i/o i/o i/o ad3 v ddp v ddp v ddp v ddp v ddp v ddp ad4 nc nc i/o i/o i/o i/o ad5 nc nc i/o i/o i/o i/o ad6 nc nc i/o i/o i/o i/o ad7 i/o i/o i/o i/o i/o i/o ad8 i/o i/o i/o i/o i/o i/o ad9 i/o i/o i/o i/o i/o i/o ad10 i/o i/o i/o i/o i/o i/o ad11 i/o i/o i/o i/o i/o i/o ad12 i/o i/o i/o i/o i/o i/o 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 73 proasic plus family flash fpgas ad13 i/o i/o i/o i/o i/o i/o ad14 i/o i/o i/o i/o i/o i/o ad15 i/o i/o i/o i/o i/o i/o ad16 i/o i/o i/o i/o i/o i/o ad17 i/o i/o i/o i/o i/o i/o ad18 i/o i/o i/o i/o i/o i/o ad19 i/o i/o i/o i/o i/o i/o ad20 nc nc i/o i/o i/o i/o ad21 tck tck tck tck tck tck ad22 v pp v pp v pp v pp v pp v pp ad23 nc nc nc i/o i/o i/o ad24 v ddp v ddp v ddp v ddp v ddp v ddp ad25 nc nc i/o i/o i/o i/o ad26 nc nc i/o i/o i/o i/o ae1 v ddp v ddp v ddp v ddp v ddp v ddp ae2 v ddp v ddp v ddp v ddp v ddp v ddp ae3 nc nc i/o i/o i/o i/o ae4 nc nc i/o i/o i/o i/o ae5 nc nc i/o i/o i/o i/o ae6 nc nc i/o i/o i/o i/o ae7 nc nc i/o i/o i/o i/o ae8 i/o i/o i/o i/o i/o i/o ae9 i/o i/o i/o i/o i/o i/o ae10 i/o i/o i/o i/o i/o i/o ae11 i/o i/o i/o i/o i/o i/o ae12 i/o i/o i/o i/o i/o i/o ae13 i/o i/o i/o i/o i/o i/o ae14 i/o i/o i/o i/o i/o i/o ae15 i/o i/o i/o i/o i/o i/o ae16 i/o i/o i/o i/o i/o i/o ae17 i/o i/o i/o i/o i/o i/o ae18 i/o i/o i/o i/o i/o i/o ae19 i/o i/o i/o i/o i/o i/o ae20 nc nc i/o i/o i/o i/o ae21 nc nc i/o i/o i/o i/o ae22 nc nc i/o i/o i/o i/o ae23 v pn v pn v pn v pn v pn v pn ae24 trst trst trst trst trst trst ae25 v ddp v ddp v ddp v ddp v ddp v ddp 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
proasic plus family flash fpgas 74 advanced v0.6 ae26 v ddp v ddp v ddp v ddp v ddp v ddp af1 v ddp v ddp v ddp v ddp v ddp v ddp af2 v ddp v ddp v ddp v ddp v ddp v ddp af3 nc nc i/o i/o i/o i/o af4 nc nc i/o i/o i/o i/o af5 nc nc i/o i/o i/o i/o af6 nc nc i/o i/o i/o i/o af7 nc nc i/o i/o i/o i/o af8 nc nc nc i/o i/o i/o af9 i/o i/o i/o i/o i/o i/o af10 i/o i/o i/o i/o i/o i/o af11 i/o i/o i/o i/o i/o i/o af12 i/o i/o i/o i/o i/o i/o af13 i/o i/o i/o i/o i/o i/o af14 i/o i/o i/o i/o i/o i/o af15 i/o i/o i/o i/o i/o i/o af16 i/o i/o i/o i/o i/o i/o af17 i/o i/o i/o i/o i/o i/o af18 nc nc i/o i/o i/o i/o af19 nc nc i/o i/o i/o i/o af20 nc nc i/o i/o i/o i/o af21 nc nc i/o i/o i/o i/o af22 nc nc i/o i/o i/o i/o af23 tdi tdi tdi tdi tdi tdi af24 nc nc i/o i/o i/o i/o af25 v ddp v ddp v ddp v ddp v ddp v ddp af26 v ddp v ddp v ddp v ddp v ddp v ddp 456-pin pbga (continued) pin number apa150 function apa300 function apa450 function apa600 function apa750 function apa1000 function
advanced v0.6 75 proasic plus family flash fpgas package assignments (continued) 144-fbga (bottom view) 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m
proasic plus family flash fpgas 76 advanced v0.6 144-fbga pin pin number apa150 function apa300 function apa450 function a1 i/o i/o i/o a2 i/o i/o i/o a3 i/o i/o i/o a4 i/o i/o i/o a5 i/o i/o i/o a6 gnd gnd gnd a7 i/o i/o i/o a8 v dd v dd v dd a9 i/o i/o i/o a10 i/o i/o i/o a11 i/o i/o i/o a12 i/o i/o i/o b1 i/o i/o i/o b2 gnd gnd gnd b3 i/o i/o i/o b4 i/o i/o i/o b5 i/o i/o i/o b6 i/o i/o i/o b7 i/o i/o i/o b8 i/o i/o i/o b9 i/o i/o i/o b10 i/o i/o i/o b11 gnd gnd gnd b12 i/o i/o i/o c1 i/o i/o i/o c2 gl gl gl c3 i/o i/o i/o c4 v dd v dd v dd c5 i/o i/o i/o c6 i/o i/o i/o c7 i/o i/o i/o c8 i/o i/o i/o c9 i/o i/o i/o c10 i/o i/o i/o c11 i/o i/o i/o c12 i/o i/o i/o d1 i/o i/o i/o d2 i/o i/o i/o d3 i/o i/o i/o d4 i/o i/o i/o d5 i/o i/o i/o d6 i/o i/o i/o d7 i/o i/o i/o d8 i/o i/o i/o d9 i/o i/o i/o d10 i/o i/o i/o d11 i/o i/o i/o d12 i/o i/o i/o e1 v dd v dd v dd e2 i/o i/o i/o e3 i/o i/o i/o e4 v ddp v ddp v ddp e5 i/o i/o i/o e6 v ddp v ddp v ddp e7 v ddp v ddp v ddp e8 avdd avdd avdd e9 v ddp v ddp v ddp e10 v dd v dd v dd e11 npecl npecl npecl e12 agnd agnd agnd f1 gl gl gl f2 agnd agnd agnd f3 i/o i/o i/o f4 i/o i/o i/o f5 gnd gnd gnd f6 gnd gnd gnd f7 gnd gnd gnd f8 i/o i/o i/o f9 gl gl gl f10 gnd gnd gnd f11 ppecl ppecl ppecl f12 gl gl gl g1 ppecl ppecl ppecl g2 gnd gnd gnd g3 avdd avdd avdd g4 npecl npecl npecl g5 gnd gnd gnd g6 gnd gnd gnd 144-fbga pin (continued) pin number apa150 function apa300 function apa450 function
advanced v0.6 77 proasic plus family flash fpgas g7 gnd gnd gnd g8 i/o i/o i/o g9 i/o i/o i/o g10 i/o i/o i/o g11 i/o i/o i/o g12 i/o i/o i/o h1 v dd v dd v dd h2 i/o i/o i/o h3 i/o i/o i/o h4 i/o i/o i/o h5 v dd v dd v dd h6 i/o i/o i/o h7 i/o i/o i/o h8 i/o i/o i/o h9 i/o i/o i/o h10 v ddp v ddp v ddp h11 i/o i/o i/o h12 v dd v dd v dd j1 i/o i/o i/o j2 i/o i/o i/o j3 v ddp v ddp v ddp j4 i/o i/o i/o j5 i/o i/o i/o j6 i/o i/o i/o j7 v dd v dd v dd j8 tck tck tck j9 i/o i/o i/o j10 tdo tdo tdo j11 i/o i/o i/o j12 i/o i/o i/o k1 i/o i/o i/o k2 i/o i/o i/o k3 i/o i/o i/o k4 i/o i/o i/o k5 i/o i/o i/o k6 i/o i/o i/o k7 gnd gnd gnd k8 i/o i/o i/o k9 i/o i/o i/o 144-fbga pin (continued) pin number apa150 function apa300 function apa450 function k10 gnd gnd gnd k11 i/o i/o i/o k12 i/o i/o i/o l1 gnd gnd gnd l2 i/o i/o i/o l3 i/o i/o i/o l4 i/o i/o i/o l5 v ddp v ddp v ddp l6 i/o i/o i/o l7 i/o i/o i/o l8 i/o i/o i/o l9 tms tms tms l10 rck rck rck l11 i/o i/o i/o l12 trst trst trst m1 i/o i/o i/o m2 i/o i/o i/o m3 i/o i/o i/o m4 i/o i/o i/o m5 i/o i/o i/o m6 i/o i/o i/o m7 i/o i/o i/o m8 i/o i/o i/o m9 tdi tdi tdi m10 v ddp v ddp v ddp m11 v pp v pp v pp m12 v pn v pn v pn 144-fbga pin (continued) pin number apa150 function apa300 function apa450 function
proasic plus family flash fpgas 78 advanced v0.6 package assignments (continued) 256-fbga (bottom view) 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a pin one corner
advanced v0.6 79 proasic plus family flash fpgas 256-pin fbga pin number apa150 function apa300 function apa450 function apa600 function a1 gnd gnd gnd gnd a2 i/o i/o i/o i/o a3 i/o i/o i/o i/o a4 i/o i/o i/o i/o a5 i/o i/o i/o i/o a6 i/o i/o i/o i/o a7 i/o i/o i/o i/o a8 i/o i/o i/o i/o a9 i/o i/o i/o i/o a10 i/o i/o i/o i/o a11 i/o i/o i/o i/o a12 i/o i/o i/o i/o a13 i/o i/o i/o i/o a14 i/o i/o i/o i/o a15 i/o i/o i/o i/o a16 gnd gnd gnd gnd b1 i/o i/o i/o i/o b2 i/o i/o i/o i/o b3 i/o i/o i/o i/o b4 i/o i/o i/o i/o b5 i/o i/o i/o i/o b6 i/o i/o i/o i/o b7 i/o i/o i/o i/o b8 i/o i/o i/o i/o b9 i/o i/o i/o i/o b10 i/o i/o i/o i/o b11 i/o i/o i/o i/o b12 i/o i/o i/o i/o b13 i/o i/o i/o i/o b14 i/o i/o i/o i/o b15 i/o i/o i/o i/o b16 i/o i/o i/o i/o c1 i/o i/o i/o i/o c2 i/o i/o i/o i/o c3 i/o i/o i/o i/o c4 i/o i/o i/o i/o c5 i/o i/o i/o i/o c6 i/o i/o i/o i/o c7 i/o i/o i/o i/o
proasic plus family flash fpgas 80 advanced v0.6 c8 i/o i/o i/o i/o c9 i/o i/o i/o i/o c10 i/o i/o i/o i/o c11 i/o i/o i/o i/o c12 i/o i/o i/o i/o c13 i/o i/o i/o i/o c14 i/o i/o i/o i/o c15 i/o i/o i/o i/o c16 i/o i/o i/o i/o d1 i/o i/o i/o i/o d2 i/o i/o i/o i/o d3 i/o i/o i/o i/o d4 i/o i/o i/o i/o d5 i/o i/o i/o i/o d6 i/o i/o i/o i/o d7 i/o i/o i/o i/o d8 i/o i/o i/o i/o d9 i/o i/o i/o i/o d10 i/o i/o i/o i/o d11 i/o i/o i/o i/o d12 i/o i/o i/o i/o d13 i/o i/o i/o i/o d14 i/o i/o i/o i/o d15 i/o i/o i/o i/o d16 i/o i/o i/o i/o e1 i/o i/o i/o i/o e2 i/o i/o i/o i/o e3 i/o i/o i/o i/o e4 i/o i/o i/o i/o e5 i/o i/o i/o i/o e6 v ddp v ddp v ddp v ddp e7 v ddp v ddp v ddp v ddp e8 i/o i/o i/o i/o e9 i/o i/o i/o i/o e10 v ddp v ddp v ddp v ddp e11 v ddp v ddp v ddp v ddp e12 i/o i/o i/o i/o e13 i/o i/o i/o i/o e14 i/o i/o i/o i/o 256-pin fbga (continued) pin number apa150 function apa300 function apa450 function apa600 function
advanced v0.6 81 proasic plus family flash fpgas e15 i/o i/o i/o i/o e16 i/o i/o i/o i/o f1 i/o i/o i/o i/o f2 i/o i/o i/o i/o f3 i/o i/o i/o i/o f4 i/o i/o i/o i/o f5 v ddp v ddp v ddp v ddp f6 gnd gnd gnd gnd f7 v dd v dd v dd v dd f8 v dd v dd v dd v dd f9 v dd v dd v dd v dd f10 v dd v dd v dd v dd f11 gnd gnd gnd gnd f12 v ddp v ddp v ddp v ddp f13 i/o i/o i/o i/o f14 i/o i/o i/o i/o f15 i/o i/o i/o i/o f16 i/o i/o i/o i/o g1 i/o i/o i/o i/o g2 i/o i/o i/o i/o g3 i/o i/o i/o i/o g4 i/o i/o i/o i/o g5 v ddp v ddp v ddp v ddp g6 v dd v dd v dd v dd g7 gnd gnd gnd gnd g8 gnd gnd gnd gnd g9 gnd gnd gnd gnd g10 gnd gnd gnd gnd g11 v dd v dd v dd v dd g12 v ddp v ddp v ddp v ddp g13 i/o i/o i/o i/o g14 i/o i/o i/o i/o g15 i/o i/o i/o i/o g16 i/o i/o i/o i/o h1 gl gl gl gl h2 npecl npecl npecl npecl h3 i/o i/o i/o i/o h4 agnd agnd agnd agnd h5 i/o i/o i/o i/o 256-pin fbga (continued) pin number apa150 function apa300 function apa450 function apa600 function
proasic plus family flash fpgas 82 advanced v0.6 h6 v dd v dd v dd v dd h7 gnd gnd gnd gnd h8 gnd gnd gnd gnd h9 gnd gnd gnd gnd h10 gnd gnd gnd gnd h11 v dd v dd v dd v dd h12 i/o i/o i/o i/o h13 i/o i/o i/o i/o h14 npecl npecl npecl npecl h15 agnd agnd agnd agnd h16glglglgl j1 gl gl gl gl j2 ppecl ppecl ppecl ppecl j3 avdd avdd avdd avdd j4 i/o i/o i/o i/o j5 i/o i/o i/o i/o j6 v dd v dd v dd v dd j7 gnd gnd gnd gnd j8 gnd gnd gnd gnd j9 gnd gnd gnd gnd j10 gnd gnd gnd gnd j11 v dd v dd v dd v dd j12 i/o i/o i/o i/o j13 ppecl ppecl ppecl ppecl j14 i/o i/o i/o i/o j15 avdd avdd avdd avdd j16glglglgl k1 i/o i/o i/o i/o k2 i/o i/o i/o i/o k3 i/o i/o i/o i/o k4 i/o i/o i/o i/o k5 v ddp v ddp v ddp v ddp k6 v dd v dd v dd v dd k7 gnd gnd gnd gnd k8 gnd gnd gnd gnd k9 gnd gnd gnd gnd k10 gnd gnd gnd gnd k11 v dd v dd v dd v dd k12 v ddp v ddp v ddp v ddp 256-pin fbga (continued) pin number apa150 function apa300 function apa450 function apa600 function
advanced v0.6 83 proasic plus family flash fpgas k13 i/o i/o i/o i/o k14 i/o i/o i/o i/o k15 i/o i/o i/o i/o k16 i/o i/o i/o i/o l1 i/o i/o i/o i/o l2 i/o i/o i/o i/o l3 i/o i/o i/o i/o l4 i/o i/o i/o i/o l5 v ddp v ddp v ddp v ddp l6 gnd gnd gnd gnd l7 v dd v dd v dd v dd l8 v dd v dd v dd v dd l9 v dd v dd v dd v dd l10 v dd v dd v dd v dd l11 gnd gnd gnd gnd l12 v ddp v ddp v ddp v ddp l13 i/o i/o i/o i/o l14 i/o i/o i/o i/o l15 i/o i/o i/o i/o l16 i/o i/o i/o i/o m1 i/o i/o i/o i/o m2 i/o i/o i/o i/o m3 i/o i/o i/o i/o m4 i/o i/o i/o i/o m5 i/o i/o i/o i/o m6 v ddp v ddp v ddp v ddp m7 v ddp v ddp v ddp v ddp m8 i/o i/o i/o i/o m9 i/o i/o i/o i/o m10 v ddp v ddp v ddp v ddp m11 v ddp v ddp v ddp v ddp m12 i/o i/o i/o i/o m13 i/o i/o i/o i/o m14 i/o i/o i/o i/o m15 i/o i/o i/o i/o m16 i/o i/o i/o i/o n1 i/o i/o i/o i/o n2 i/o i/o i/o i/o n3 i/o i/o i/o i/o 256-pin fbga (continued) pin number apa150 function apa300 function apa450 function apa600 function
proasic plus family flash fpgas 84 advanced v0.6 n4 i/o i/o i/o i/o n5 i/o i/o i/o i/o n6 i/o i/o i/o i/o n7 i/o i/o i/o i/o n8 i/o i/o i/o i/o n9 i/o i/o i/o i/o n10 i/o i/o i/o i/o n11 i/o i/o i/o i/o n12 i/o i/o i/o i/o n13 i/o i/o i/o i/o n14 rck rck rck rck n15 i/o i/o i/o i/o n16 i/o i/o i/o i/o p1 i/o i/o i/o i/o p2 i/o i/o i/o i/o p3 i/o i/o i/o i/o p4 i/o i/o i/o i/o p5 i/o i/o i/o i/o p6 i/o i/o i/o i/o p7 i/o i/o i/o i/o p8 i/o i/o i/o i/o p9 i/o i/o i/o i/o p10 i/o i/o i/o i/o p11 i/o i/o i/o i/o p12 i/o i/o i/o i/o p13 tck tck tck tck p14 v pp v pp v pp v pp p15 trst trst trst trst p16 i/o i/o i/o i/o r1 i/o i/o i/o i/o r2 i/o i/o i/o i/o r3 i/o i/o i/o i/o r4 i/o i/o i/o i/o r5 i/o i/o i/o i/o r6 i/o i/o i/o i/o r7 i/o i/o i/o i/o r8 i/o i/o i/o i/o r9 i/o i/o i/o i/o r10 i/o i/o i/o i/o 256-pin fbga (continued) pin number apa150 function apa300 function apa450 function apa600 function
advanced v0.6 85 proasic plus family flash fpgas r11 i/o i/o i/o i/o r12 i/o i/o i/o i/o r13 i/o i/o i/o i/o r14 tdi tdi tdi tdi r15 v pn v pn v pn v pn r16 tdo tdo tdo tdo t1 gnd gnd gnd gnd t2 i/o i/o i/o i/o t3 i/o i/o i/o i/o t4 i/o i/o i/o i/o t5 i/o i/o i/o i/o t6 i/o i/o i/o i/o t7 i/o i/o i/o i/o t8 i/o i/o i/o i/o t9 i/o i/o i/o i/o t10 i/o i/o i/o i/o t11 i/o i/o i/o i/o t12 i/o i/o i/o i/o t13 i/o i/o i/o i/o t14 i/o i/o i/o i/o t15 tms tms tms tms t16 gnd gnd gnd gnd 256-pin fbga (continued) pin number apa150 function apa300 function apa450 function apa600 function
proasic plus family flash fpgas 86 advanced v0.6 package pin assignments (continued) 676-pin fbga (bottom view) 1 2 3 5 6 7 8 9 10 11 15 14 13 12 16 17 18 19 20 21 22 23 4 24 25 26 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af
advanced v0.6 87 proasic plus family flash fpgas 676-fbga pin pin number apa600 function apa750 function a1 gnd gnd a2 gnd gnd a3 i/o i/o a4 i/o i/o a5 i/o i/o a6 i/o i/o a7 i/o i/o a8 i/o i/o a9 i/o i/o a10 i/o i/o a11 i/o i/o a12 i/o i/o a13 i/o i/o a14 i/o i/o a15 i/o i/o a16 i/o i/o a17 i/o i/o a18 i/o i/o a19 i/o i/o a20 i/o i/o a21 i/o i/o a22 i/o i/o a23 i/o i/o a24 i/o i/o a25 gnd gnd a26 gnd gnd b1 gnd gnd b2 gnd gnd b3 gnd gnd b4 gnd gnd b5 i/o i/o b6 i/o i/o b7 i/o i/o b8 i/o i/o b9 i/o i/o b10 i/o i/o b11 i/o i/o b12 i/o i/o b13 i/o i/o b14 i/o i/o b15 i/o i/o b16 i/o i/o b17 i/o i/o b18 i/o i/o b19 i/o i/o b20 i/o i/o b21 i/o i/o b22 i/o i/o b23 i/o i/o b24 i/o i/o b25 gnd gnd b26 gnd gnd c1 gnd gnd c2 gnd gnd c3 gnd gnd c4 gnd gnd c5 i/o i/o c6 i/o i/o c7 i/o i/o c8 i/o i/o c9 i/o i/o c10 i/o i/o c11 i/o i/o c12 i/o i/o c13 i/o i/o c14 i/o i/o c15 i/o i/o c16 i/o i/o c17 i/o i/o c18 i/o i/o c19 i/o i/o c20 i/o i/o c21 i/o i/o c22 i/o i/o c23 i/o i/o c24 i/o i/o c25 i/o i/o c26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
proasic plus family flash fpgas 88 advanced v0.6 d1 i/o i/o d2 i/o i/o d3 gnd gnd d4 i/o i/o d5 i/o i/o d6 i/o i/o d7 i/o i/o d8 i/o i/o d9 i/o i/o d10 i/o i/o d11 i/o i/o d12 i/o i/o d13 i/o i/o d14 i/o i/o d15 i/o i/o d16 i/o i/o d17 i/o i/o d18 i/o i/o d19 i/o i/o d20 i/o i/o d21 i/o i/o d22 i/o i/o d23 i/o i/o d24 i/o i/o d25 i/o i/o d26 i/o i/o e1 i/o i/o e2 i/o i/o e3 i/o i/o e4 i/o i/o e5 i/o i/o e6 i/o i/o e7 i/o i/o e8 i/o i/o e9 i/o i/o e10 i/o i/o e11 i/o i/o e12 i/o i/o e13 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function e14 i/o i/o e15 i/o i/o e16 i/o i/o e17 i/o i/o e18 i/o i/o e19 i/o i/o e20 i/o i/o e21 i/o i/o e22 i/o i/o e23 i/o i/o e24 i/o i/o e25 i/o i/o e26 i/o i/o f1 i/o i/o f2 i/o i/o f3 i/o i/o f4 i/o i/o f5 gnd gnd f6 i/o i/o f7 nc nc f8 i/o i/o f9 i/o i/o f10 i/o i/o f11 i/o i/o f12 i/o i/o f13 i/o i/o f14 i/o i/o f15 i/o i/o f16 i/o i/o f17 i/o i/o f18 i/o i/o f19 i/o i/o f20 i/o i/o f21 i/o i/o f22 i/o i/o f23 i/o i/o f24 i/o i/o f25 i/o i/o f26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
advanced v0.6 89 proasic plus family flash fpgas g1 i/o i/o g2 i/o i/o g3 i/o i/o g4 i/o i/o g5 i/o i/o g6 i/o i/o g7 i/o i/o g8 v dd v dd g9 nc nc g10 i/o i/o g11 nc nc g12 i/o i/o g13 nc nc g14 i/o i/o g15 nc nc g16 i/o i/o g17 nc nc g18 i/o i/o g19 v ddp v ddp g20 nc nc g21 i/o i/o g22 i/o i/o g23 i/o i/o g24 i/o i/o g25 i/o i/o g26 i/o i/o h1 i/o i/o h2 i/o i/o h3 i/o i/o h4 i/o i/o h5 i/o i/o h6 i/o i/o h7 v ddp v ddp h8 v dd v dd h9 v ddp v ddp h10 v ddp v ddp h11 v ddp v ddp h12 v ddp v ddp h13 v ddp v ddp 676-fbga pin (continued) pin number apa600 function apa750 function h14 v ddp v ddp h15 v ddp v ddp h16 v ddp v ddp h17 v ddp v ddp h18 v ddp v ddp h19 v dd v dd h20 v dd v dd h21 i/o i/o h22 i/o i/o h23 i/o i/o h24 i/o i/o h25 i/o i/o h26 i/o i/o j1 i/o i/o j2 i/o i/o j3 i/o i/o j4 i/o i/o j5 i/o i/o j6 i/o i/o j7 nc nc j8 v ddp v ddp j9 v dd v dd j10 v dd v dd j11 v dd v dd j12 v dd v dd j13 v dd v dd j14 v dd v dd j15 v dd v dd j16 v dd v dd j17 v dd v dd j18 v dd v dd j19 v ddp v ddp j20 nc nc j21 i/o i/o j22 i/o i/o j23 i/o i/o j24 i/o i/o j25 i/o i/o j26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
proasic plus family flash fpgas 90 advanced v0.6 k1 i/o i/o k2 i/o i/o k3 i/o i/o k4 i/o i/o k5 i/o i/o k6 i/o i/o k7 i/o i/o k8 v ddp v ddp k9 v dd v dd k10 gnd gnd k11 gnd gnd k12 gnd gnd k13 gnd gnd k14 gnd gnd k15 gnd gnd k16 gnd gnd k17 gnd gnd k18 v dd v dd k19 v ddp v ddp k20 i/o i/o k21 i/o i/o k22 i/o i/o k23 i/o i/o k24 i/o i/o k25 i/o i/o k26 i/o i/o l1 i/o i/o l2 i/o i/o l3 i/o i/o l4 i/o i/o l5 i/o i/o l6 i/o i/o l7 nc nc l8 v ddp v ddp l9 v dd v dd l10 gnd gnd l11 gnd gnd l12 gnd gnd l13 gnd gnd 676-fbga pin (continued) pin number apa600 function apa750 function l14 gnd gnd l15 gnd gnd l16 gnd gnd l17 gnd gnd l18 v dd v dd l19 v ddp v ddp l20 nc nc l21 i/o i/o l22 i/o i/o l23 i/o i/o l24 i/o i/o l25 i/o i/o l26 i/o i/o m1 i/o i/o m2 i/o i/o m3 i/o i/o m4 i/o i/o m5 i/o i/o m6 i/o i/o m7 i/o i/o m8 v ddp v ddp m9 v dd v dd m10 gnd gnd m11 gnd gnd m12 gnd gnd m13 gnd gnd m14 gnd gnd m15 gnd gnd m16 gnd gnd m17 gnd gnd m18 v dd v dd m19 v ddp v ddp m20 i/o i/o m21 i/o i/o m22 i/o i/o m23 i/o i/o m24 i/o i/o m25 i/o i/o m26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
advanced v0.6 91 proasic plus family flash fpgas n1 gl gl n2 agnd agnd n3 i/o i/o n4 i/o i/o n5 npecl npecl n6 i/o i/o n7 nc nc n8 v ddp v ddp n9 v dd v dd n10 gnd gnd n11 gnd gnd n12 gnd gnd n13 gnd gnd n14 gnd gnd n15 gnd gnd n16 gnd gnd n17 gnd gnd n18 v dd v dd n19 v ddp v ddp n20 nc nc n21 i/o i/o n22 gl gl n23 i/o i/o n24 npecl npecl n25 gl gl n26 i/o i/o p1 gl gl p2 avdd avdd p3 i/o i/o p4 i/o i/o p5 ppecl ppecl p6 i/o i/o p7 i/o i/o p8 v ddp v ddp p9 v dd v dd p10 gnd gnd p11 gnd gnd p12 gnd gnd p13 gnd gnd 676-fbga pin (continued) pin number apa600 function apa750 function p14 gnd gnd p15 gnd gnd p16 gnd gnd p17 gnd gnd p18 v dd v dd p19 v ddp v ddp p20 i/o i/o p21 i/o i/o p22 i/o i/o p23 i/o i/o p24 ppecl ppecl p25 avdd avdd p26 agnd agnd r1 i/o i/o r2 i/o i/o r3 i/o i/o r4 i/o i/o r5 i/o i/o r6 i/o i/o r7 nc nc r8 v ddp v ddp r9 v dd v dd r10 gnd gnd r11 gnd gnd r12 gnd gnd r13 gnd gnd r14 gnd gnd r15 gnd gnd r16 gnd gnd r17 gnd gnd r18 v dd v dd r19 v ddp v ddp r20 nc nc r21 i/o i/o r22 i/o i/o r23 i/o i/o r24 i/o i/o r25 i/o i/o r26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
proasic plus family flash fpgas 92 advanced v0.6 t1 i/o i/o t2 i/o i/o t3 i/o i/o t4 i/o i/o t5 i/o i/o t6 i/o i/o t7 i/o i/o t8 v ddp v ddp t9 v dd v dd t10 gnd gnd t11 gnd gnd t12 gnd gnd t13 gnd gnd t14 gnd gnd t15 gnd gnd t16 gnd gnd t17 gnd gnd t18 v dd v dd t19 v ddp v ddp t20 i/o i/o t21 i/o i/o t22 i/o i/o t23 i/o i/o t24 i/o i/o t25 i/o i/o t26 i/o i/o u1 i/o i/o u2 i/o i/o u3 i/o i/o u4 i/o i/o u5 i/o i/o u6 i/o i/o u7 nc nc u8 v ddp v ddp u9 v dd v dd u10 gnd gnd u11 gnd gnd u12 gnd gnd u13 gnd gnd 676-fbga pin (continued) pin number apa600 function apa750 function u14 gnd gnd u15 gnd gnd u16 gnd gnd u17 gnd gnd u18 v dd v dd u19 v ddp v ddp u20 nc nc u21 i/o i/o u22 i/o i/o u23 i/o i/o u24 i/o i/o u25 i/o i/o u26 i/o i/o v1 i/o i/o v2 i/o i/o v3 i/o i/o v4 i/o i/o v5 i/o i/o v6 i/o i/o v7 i/o i/o v8 v ddp v ddp v9 v dd v dd v10 v dd v dd v11 v dd v dd v12 v dd v dd v13 v dd v dd v14 v dd v dd v15 v dd v dd v16 v dd v dd v17 v dd v dd v18 v dd v dd v19 v ddp v ddp v20 i/o i/o v21 i/o i/o v22 i/o i/o v23 i/o i/o v24 i/o i/o v25 i/o i/o v26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
advanced v0.6 93 proasic plus family flash fpgas w1 i/o i/o w2 i/o i/o w3 i/o i/o w4 i/o i/o w5 i/o i/o w6 i/o i/o w7 v dd v dd w8 v dd v dd w9 v ddp v ddp w10 v ddp v ddp w11 v ddp v ddp w12 v ddp v ddp w13 v ddp v ddp w14 v ddp v ddp w15 v ddp v ddp w16 v ddp v ddp w17 v ddp v ddp w18 v ddp v ddp w19 v dd v dd w20 v ddp v ddp w21 i/o i/o w22 i/o i/o w23 i/o i/o w24 i/o i/o w25 i/o i/o w26 i/o i/o y1 i/o i/o y2 i/o i/o y3 i/o i/o y4 i/o i/o y5 i/o i/o y6 i/o i/o y7 i/o i/o y8 v ddp v ddp y9 nc nc y10 i/o i/o y11 nc nc y12 i/o i/o y13 nc nc 676-fbga pin (continued) pin number apa600 function apa750 function y14 i/o i/o y15 nc nc y16 i/o i/o y17 nc nc y18 i/o i/o y19 v dd v dd y20 v pp v pp y21 i/o i/o y22 i/o i/o y23 i/o i/o y24 i/o i/o y25 i/o i/o y26 i/o i/o aa1 i/o i/o aa2 i/o i/o aa3 i/o i/o aa4 i/o i/o aa5 i/o i/o aa6 gnd gnd aa7 i/o i/o aa8 i/o i/o aa9 i/o i/o aa10 i/o i/o aa11 i/o i/o aa12 i/o i/o aa13 i/o i/o aa14 i/o i/o aa15 i/o i/o aa16 i/o i/o aa17 i/o i/o aa18 i/o i/o aa19 i/o i/o aa20 i/o i/o aa21 tdo tdo aa22 gnd gnd aa23 gnd gnd aa24 i/o i/o aa25 i/o i/o aa26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
proasic plus family flash fpgas 94 advanced v0.6 ab1 i/o i/o ab2 i/o i/o ab3 i/o i/o ab4 i/o i/o ab5 i/o i/o ab6 gnd gnd ab7 gnd gnd ab8 i/o i/o ab9 i/o i/o ab10 i/o i/o ab11 i/o i/o ab12 i/o i/o ab13 i/o i/o ab14 i/o i/o ab15 i/o i/o ab16 i/o i/o ab17 i/o i/o ab18 i/o i/o ab19 i/o i/o ab20 i/o i/o ab21 tck tck ab22 trst trst ab23 i/o i/o ab24 i/o i/o ab25 i/o i/o ab26 i/o i/o ac1 i/o i/o ac2 i/o i/o ac3 i/o i/o ac4 i/o i/o ac5 gnd gnd ac6 i/o i/o ac7 i/o i/o ac8 i/o i/o ac9 gnd gnd ac10 i/o i/o ac11 i/o i/o ac12 i/o i/o ac13 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function ac14 i/o i/o ac15 i/o i/o ac16 i/o i/o ac17 i/o i/o ac18 i/o i/o ac19 i/o i/o ac20 i/o i/o ac21 i/o i/o ac22 tms tms ac23 rck rck ac24 i/o i/o ac25 i/o i/o ac26 i/o i/o ad1 i/o i/o ad2 i/o i/o ad3 i/o i/o ad4 i/o i/o ad5 i/o i/o ad6 i/o i/o ad7 i/o i/o ad8 i/o i/o ad9 i/o i/o ad10 i/o i/o ad11 i/o i/o ad12 i/o i/o ad13 i/o i/o ad14 i/o i/o ad15 i/o i/o ad16 i/o i/o ad17 i/o i/o ad18 i/o i/o ad19 i/o i/o ad20 i/o i/o ad21 i/o i/o ad22 i/o i/o ad23 tdi tdi ad24 v pn v pn ad25 i/o i/o ad26 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function
advanced v0.6 95 proasic plus family flash fpgas ae1 gnd gnd ae2 gnd gnd ae3 gnd gnd ae4 i/o i/o ae5 i/o i/o ae6 i/o i/o ae7 i/o i/o ae8 i/o i/o ae9 i/o i/o ae10 i/o i/o ae11 i/o i/o ae12 i/o i/o ae13 i/o i/o ae14 i/o i/o ae15 i/o i/o ae16 i/o i/o ae17 i/o i/o ae18 i/o i/o ae19 i/o i/o ae20 i/o i/o ae21 i/o i/o ae22 i/o i/o ae23 i/o i/o ae24 i/o i/o ae25 gnd gnd ae26 gnd gnd af1 gnd gnd af2 gnd gnd af3 gnd gnd af4 gnd gnd af5 i/o i/o af6 i/o i/o af7 i/o i/o af8 i/o i/o af9 i/o i/o af10 i/o i/o af11 i/o i/o af12 i/o i/o af13 i/o i/o 676-fbga pin (continued) pin number apa600 function apa750 function af14 i/o i/o af15 i/o i/o af16 i/o i/o af17 i/o i/o af18 i/o i/o af19 i/o i/o af20 i/o i/o af21 i/o i/o af22 i/o i/o af23 i/o i/o af24 i/o i/o af25 gnd gnd af26 gnd gnd 676-fbga pin (continued) pin number apa600 function apa750 function
proasic plus family flash fpgas 96 advanced v0.6 package pin assignments (continued) 896-pin fbga (bottom view) a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
advanced v0.6 97 proasic plus family flash fpgas 896 fbga pin pin number apa750 function apa1000 function a2 gnd gnd a3 gnd gnd a4 i/o i/o a5 gnd gnd a6 i/o i/o a7 gnd gnd a8 i/o i/o a9 i/o i/o a10 i/o i/o a11 i/o i/o a12 i/o i/o a13 i/o i/o a14 i/o i/o a15 i/o i/o a16 i/o i/o a17 i/o i/o a18 i/o i/o a19 i/o i/o a20 i/o i/o a21 i/o i/o a22 i/o i/o a23 i/o i/o a24 gnd gnd a25 i/o i/o a26 gnd gnd a27 i/o i/o a28 gnd gnd a29 gnd gnd b1 gnd gnd b2 gnd gnd b3 i/o i/o b4 v dd v dd b5 i/o i/o b6 v dd v dd b7 i/o i/o b8 i/o i/o b9 i/o i/o b10 i/o i/o b11 i/o i/o b12 i/o i/o b13 i/o i/o b14 i/o i/o b15 i/o i/o b16 i/o i/o b17 i/o i/o b18 i/o i/o b19 i/o i/o b20 i/o i/o b21 i/o i/o b22 i/o i/o b23 i/o i/o b24 i/o i/o b25 v dd v dd b26 i/o i/o b27 v dd v dd b28 i/o i/o b29 gnd gnd b30 gnd gnd c1 gnd gnd c2 i/o i/o c3 v dd v dd c4 i/o i/o c5 v ddp v ddp c6 i/o i/o c7 i/o i/o c8 i/o i/o c9 i/o i/o c10 i/o i/o c11 i/o i/o c12 i/o i/o c13 i/o i/o c14 i/o i/o c15 i/o i/o c16 i/o i/o c17 i/o i/o c18 i/o i/o c19 i/o i/o c20 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
proasic plus family flash fpgas 98 advanced v0.6 c21 i/o i/o c22 i/o i/o c23 i/o i/o c24 i/o i/o c25 i/o i/o c26 v ddp v ddp c27 i/o i/o c28 v dd v dd c29 nc i/o c30 gnd gnd d1 i/o i/o d2 v dd v dd d3 i/o i/o d4 gnd gnd d5 i/o i/o d6 i/o i/o d7 i/o i/o d8 i/o i/o d9 i/o i/o d10 i/o i/o d11 i/o i/o d12 i/o i/o d13 i/o i/o d14 i/o i/o d15 i/o i/o d16 i/o i/o d17 i/o i/o d18 i/o i/o d19 i/o i/o d20 i/o i/o d21 i/o i/o d22 i/o i/o d23 i/o i/o d24 i/o i/o d25 i/o i/o d26 i/o i/o d27 gnd gnd d28 i/o i/o d29 v dd v dd 896 fbga pin (continued) pin number apa750 function apa1000 function d30 i/o i/o e1 gnd gnd e2 i/o i/o e3 v ddp v ddp e4 i/o i/o e5 v dd v dd e6 i/o i/o e7 v ddp v ddp e8 i/o i/o e9 i/o i/o e10 i/o i/o e11 i/o i/o e12 i/o i/o e13 i/o i/o e14 i/o i/o e15 i/o i/o e16 i/o i/o e17 i/o i/o e18 i/o i/o e19 i/o i/o e20 i/o i/o e21 i/o i/o e22 i/o i/o e23 i/o i/o e24 v ddp v ddp e25 i/o i/o e26 v dd v dd e27 i/o i/o e28 v ddp v ddp e29 i/o i/o e30 gnd gnd f1 i/o i/o f2 v dd v dd f3 i/o i/o f4 i/o i/o f5 i/o i/o f6 gnd gnd f7 i/o i/o f8 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
advanced v0.6 99 proasic plus family flash fpgas f9 i/o i/o f10 i/o i/o f11 i/o i/o f12 i/o i/o f13 i/o i/o f14 i/o i/o f15 i/o i/o f16 i/o i/o f17 i/o i/o f18 i/o i/o f19 i/o i/o f20 i/o i/o f21 i/o i/o f22 i/o i/o f23 i/o i/o f24 i/o i/o f25 gnd gnd f26 i/o i/o f27 i/o i/o f28 i/o i/o f29 v dd v dd f30 i/o i/o g1 gnd gnd g2 i/o i/o g3 i/o i/o g4 i/o i/o g5 v ddp v ddp g6 i/o i/o g7 v dd v dd g8 i/o i/o g9 v ddp v ddp g10 i/o i/o g11 i/o i/o g12 i/o i/o g13 i/o i/o g14 i/o i/o g15 i/o i/o g16 i/o i/o g17 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function g18 i/o i/o g19 i/o i/o g20 i/o i/o g21 i/o i/o g22 v ddp v ddp g23 i/o i/o g24 v dd v dd g25 i/o i/o g26 v ddp v ddp g27 i/o i/o g28 i/o i/o g29 i/o i/o g30 gnd gnd h1 i/o i/o h2 i/o i/o h3 i/o i/o h4 i/o i/o h5 i/o i/o h6 i/o i/o h7 i/o i/o h8 gnd gnd h9 nc i/o h10 nc i/o h11 nc i/o h12 nc i/o h13 nc i/o h14 nc i/o h15 nc i/o h16 nc i/o h17 nc i/o h18 nc i/o h19 nc i/o h20 nc i/o h21 nc i/o h22 nc i/o h23 gnd gnd h24 i/o i/o h25 i/o i/o h26 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
proasic plus family flash fpgas 100 advanced v0.6 h27 i/o i/o h28 i/o i/o h29 i/o i/o h30 i/o i/o j1 i/o i/o j2 i/o i/o j3 i/o i/o j4 i/o i/o j5 i/o i/o j6 i/o i/o j7 v ddp v ddp j8 i/o i/o j9 v dd v dd j10 nc i/o j11 nc i/o j12 nc i/o j13 nc i/o j14 nc i/o j15 nc i/o j16 nc i/o j17 nc i/o j18 nc i/o j19 nc i/o j20 nc i/o j21 nc i/o j22 v dd v dd j23 i/o i/o j24 v ddp v ddp j25 i/o i/o j26 i/o i/o j27 i/o i/o j28 i/o i/o j29 i/o i/o j30 i/o i/o k1 i/o i/o k2 i/o i/o k3 i/o i/o k4 i/o i/o k5 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function k6 i/o i/o k7 i/o i/o k8 i/o i/o k9 nc i/o k10 v dd v dd k11 nc i/o k12 v ddp v ddp k13 v ddp v ddp k14 v ddp v ddp k15 v ddp v ddp k16 v ddp v ddp k17 v ddp v ddp k18 v ddp v ddp k19 v ddp v ddp k20 nc i/o k21 v dd v dd k22 nc i/o k23 i/o i/o k24 i/o i/o k25 i/o i/o k26 i/o i/o k27 i/o i/o k28 i/o i/o k29 i/o i/o k30 i/o i/o l1 i/o i/o l2 i/o i/o l3 i/o i/o l4 i/o i/o l5 i/o i/o l6 i/o i/o l7 i/o i/o l8 i/o i/o l9 nc i/o l10 nc i/o l11 v dd v dd l12 v dd v dd l13 v dd v dd l14 v dd v dd 896 fbga pin (continued) pin number apa750 function apa1000 function
advanced v0.6 101 proasic plus family flash fpgas l15 v dd v dd l16 v dd v dd l17 v dd v dd l18 v dd v dd l19 v dd v dd l20 v dd v dd l21 nc i/o l22 nc i/o l23 i/o i/o l24 i/o i/o l25 i/o i/o l26 i/o i/o l27 i/o i/o l28 i/o i/o l29 i/o i/o l30 i/o i/o m1 i/o i/o m2 i/o i/o m3 i/o i/o m4 i/o i/o m5 i/o i/o m6 i/o i/o m7 i/o i/o m8 i/o i/o m9 nc i/o m10 v ddp v ddp m11 v dd v dd m12 gnd gnd m13 gnd gnd m14 gnd gnd m15 gnd gnd m16 gnd gnd m17 gnd gnd m18 gnd gnd m19 gnd gnd m20 v dd v dd m21 v ddp v ddp m22 nc i/o m23 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function m24 i/o i/o m25 i/o i/o m26 i/o i/o m27 i/o i/o m28 i/o i/o m29 i/o i/o m30 i/o i/o n1 i/o i/o n2 i/o i/o n3 i/o i/o n4 i/o i/o n5 i/o i/o n6 i/o i/o n7 i/o i/o n8 i/o i/o n9 nc i/o n10 v ddp v ddp n11 v dd v dd n12 gnd gnd n13 gnd gnd n14 gnd gnd n15 gnd gnd n16 gnd gnd n17 gnd gnd n18 gnd gnd n19 gnd gnd n20 v dd v dd n21 v ddp v ddp n22 nc i/o n23 i/o i/o n24 i/o i/o n25 i/o i/o n26 i/o i/o n27 i/o i/o n28 i/o i/o n29 i/o i/o n30 i/o i/o p1 i/o i/o p2 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
proasic plus family flash fpgas 102 advanced v0.6 p3 i/o i/o p4 i/o i/o p5 i/o i/o p6 i/o i/o p7 i/o i/o p8 i/o i/o p9 i/o i/o p10 v ddp v ddp p11 v dd v dd p12 gnd gnd p13 gnd gnd p14 gnd gnd p15 gnd gnd p16 gnd gnd p17 gnd gnd p18 gnd gnd p19 gnd gnd p20 v dd v dd p21 v ddp v ddp p22 i/o i/o p23 i/o i/o p24 i/o i/o p25 i/o i/o p26 i/o i/o p27 i/o i/o p28 i/o i/o p29 i/o i/o p30 i/o i/o r1 i/o i/o r2 i/o i/o r3 agnd agnd r4 npecl npecl r5 gl gl r6 i/o i/o r7 i/o i/o r8 i/o i/o r9 nc i/o r10 v ddp v ddp r11 v dd v dd 896 fbga pin (continued) pin number apa750 function apa1000 function r12 gnd gnd r13 gnd gnd r14 gnd gnd r15 gnd gnd r16 gnd gnd r17 gnd gnd r18 gnd gnd r19 gnd gnd r20 v dd v dd r21 v ddp v ddp r22 i/o i/o r23 i/o i/o r24 i/o i/o r25 i/o i/o r26 i/o i/o r27 npecl npecl r28 agnd agnd r29 i/o i/o r30 i/o i/o t1 i/o i/o t2 avdd avdd t3 gl gl t4 ppecl ppecl t5 i/o i/o t6 i/o i/o t7 i/o i/o t8 i/o i/o t9 i/o i/o t10 v ddp v ddp t11 v dd v dd t12 gnd gnd t13 gnd gnd t14 gnd gnd t15 gnd gnd t16 gnd gnd t17 gnd gnd t18 gnd gnd t19 gnd gnd t20 v dd v dd 896 fbga pin (continued) pin number apa750 function apa1000 function
advanced v0.6 103 proasic plus family flash fpgas t21 v ddp v ddp t22 i/o i/o t23 i/o i/o t24 i/o i/o t25 i/o i/o t26 ppecl ppecl t27 gl gl t28 gl gl t29 avdd avdd t30 i/o i/o u1 i/o i/o u2 i/o i/o u3 i/o i/o u4 i/o i/o u5 i/o i/o u6 i/o i/o u7 i/o i/o u8 i/o i/o u9 nc i/o u10 v ddp v ddp u11 v dd v dd u12 gnd gnd u13 gnd gnd u14 gnd gnd u15 gnd gnd u16 gnd gnd u17 gnd gnd u18 gnd gnd u19 gnd gnd u20 v dd v dd u21 v ddp v ddp u22 nc i/o u23 i/o i/o u24 i/o i/o u25 i/o i/o u26 i/o i/o u27 i/o i/o u28 i/o i/o u29 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function u30 i/o i/o v1 i/o i/o v2 i/o i/o v3 i/o i/o v4 i/o i/o v5 i/o i/o v6 i/o i/o v7 i/o i/o v8 i/o i/o v9 nc i/o v10 v ddp v ddp v11 v dd v dd v12 gnd gnd v13 gnd gnd v14 gnd gnd v15 gnd gnd v16 gnd gnd v17 gnd gnd v18 gnd gnd v19 gnd gnd v20 v dd v dd v21 v ddp v ddp v22 nc i/o v23 i/o i/o v24 i/o i/o v25 i/o i/o v26 i/o i/o v27 i/o i/o v28 i/o i/o v29 i/o i/o v30 i/o i/o w1 i/o i/o w2 i/o i/o w3 i/o i/o w4 i/o i/o w5 i/o i/o w6 i/o i/o w7 i/o i/o w8 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
proasic plus family flash fpgas 104 advanced v0.6 w9 nc i/o w10 v ddp v ddp w11 v dd v dd w12 gnd gnd w13 gnd gnd w14 gnd gnd w15 gnd gnd w16 gnd gnd w17 gnd gnd w18 gnd gnd w19 gnd gnd w20 v dd v dd w21 v ddp v ddp w22 nc i/o w23 i/o i/o w24 i/o i/o w25 i/o i/o w26 i/o i/o w27 i/o i/o w28 i/o i/o w29 i/o i/o w30 i/o i/o y1 i/o i/o y2 i/o i/o y3 i/o i/o y4 i/o i/o y5 i/o i/o y6 i/o i/o y7 i/o i/o y8 i/o i/o y9 nc i/o y10 nc i/o y11 v dd v dd y12 v dd v dd y13 v dd v dd y14 v dd v dd y15 v dd v dd y16 v dd v dd y17 v dd v dd 896 fbga pin (continued) pin number apa750 function apa1000 function y18 v dd v dd y19 v dd v dd y20 v dd v dd y21 nc i/o y22 nc i/o y23 i/o i/o y24 i/o i/o y25 i/o i/o y26 i/o i/o y27 i/o i/o y28 i/o i/o y29 i/o i/o y30 i/o i/o aa1 i/o i/o aa2 i/o i/o aa3 i/o i/o aa4 i/o i/o aa5 i/o i/o aa6 i/o i/o aa7 i/o i/o aa8 i/o i/o aa9 nc i/o aa10 v dd v dd aa11 nc i/o aa12 v ddp v ddp aa13 v ddp v ddp aa14 v ddp v ddp aa15 v ddp v ddp aa16 v ddp v ddp aa17 v ddp v ddp aa18 v ddp v ddp aa19 v ddp v ddp aa20 nc i/o aa21 v dd v dd aa22 nc i/o aa23 i/o i/o aa24 i/o i/o aa25 i/o i/o aa26 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
advanced v0.6 105 proasic plus family flash fpgas aa27 i/o i/o aa28 i/o i/o aa29 i/o i/o aa30 i/o i/o ab1 i/o i/o ab2 i/o i/o ab3 i/o i/o ab4 i/o i/o ab5 i/o i/o ab6 i/o i/o ab7 v ddp v ddp ab8 i/o i/o ab9 v dd v dd ab10 nc i/o ab11 nc i/o ab12 nc i/o ab13 nc i/o ab14 nc i/o ab15 nc i/o ab16 nc i/o ab17 nc i/o ab18 nc i/o ab19 nc i/o ab20 nc i/o ab21 nc i/o ab22 v dd v dd ab23 i/o i/o ab24 v ddp v ddp ab25 i/o i/o ab26 i/o i/o ab27 i/o i/o ab28 i/o i/o ab29 i/o i/o ab30 i/o i/o ac1 i/o i/o ac2 i/o i/o ac3 i/o i/o ac4 i/o i/o ac5 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function ac6 i/o i/o ac7 i/o i/o ac8 gnd gnd ac9 nc i/o ac10 nc i/o ac11 nc i/o ac12 nc i/o ac13 nc i/o ac14 nc i/o ac15 nc i/o ac16 nc i/o ac17 nc i/o ac18 nc i/o ac19 nc i/o ac20 nc i/o ac21 nc i/o ac22 nc i/o ac23 gnd gnd ac24 i/o i/o ac25 i/o i/o ac26 i/o i/o ac27 i/o i/o ac28 i/o i/o ac29 i/o i/o ac30 i/o i/o ad1 gnd gnd ad2 i/o i/o ad3 i/o i/o ad4 i/o i/o ad5 v ddp v ddp ad6 i/o i/o ad7 v dd v dd ad8 i/o i/o ad9 v ddp v ddp ad10 i/o i/o ad11 i/o i/o ad12 i/o i/o ad13 i/o i/o ad14 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
proasic plus family flash fpgas 106 advanced v0.6 ad15 i/o i/o ad16 i/o i/o ad17 i/o i/o ad18 i/o i/o ad19 i/o i/o ad20 i/o i/o ad21 i/o i/o ad22 v ddp v ddp ad23 tck tck ad24 v dd v dd ad25 trst trst ad26 v ddp v ddp ad27 i/o i/o ad28 i/o i/o ad29 i/o i/o ad30 gnd gnd ae1 i/o i/o ae2 v dd v dd ae3 i/o i/o ae4 i/o i/o ae5 i/o i/o ae6 gnd gnd ae7 i/o i/o ae8 i/o i/o ae9 i/o i/o ae10 i/o i/o ae11 i/o i/o ae12 i/o i/o ae13 i/o i/o ae14 i/o i/o ae15 i/o i/o ae16 i/o i/o ae17 i/o i/o ae18 i/o i/o ae19 i/o i/o ae20 i/o i/o ae21 i/o i/o ae22 i/o i/o ae23 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function ae24 i/o i/o ae25 gnd gnd ae26 i/o i/o ae27 i/o i/o ae28 i/o i/o ae29 v dd v dd ae30 i/o i/o af1 gnd gnd af2 i/o i/o af3 v ddp v ddp af4 i/o i/o af5 v dd v dd af6 i/o i/o af7 v ddp v ddp af8 i/o i/o af9 i/o i/o af10 i/o i/o af11 i/o i/o af12 i/o i/o af13 i/o i/o af14 i/o i/o af15 i/o i/o af16 i/o i/o af17 i/o i/o af18 i/o i/o af19 i/o i/o af20 i/o i/o af21 i/o i/o af22 i/o i/o af23 i/o i/o af24 v ddp v ddp af25 i/o i/o af26 v dd v dd af27 tdo tdo af28 v ddp v ddp af29 v pn v pn af30 gnd gnd ag1 i/o i/o ag2 v dd v dd 896 fbga pin (continued) pin number apa750 function apa1000 function
advanced v0.6 107 proasic plus family flash fpgas ag3 i/o i/o ag4 gnd gnd ag5 i/o i/o ag6 i/o i/o ag7 i/o i/o ag8 i/o i/o ag9 i/o i/o ag10 i/o i/o ag11 i/o i/o ag12 i/o i/o ag13 i/o i/o ag14 i/o i/o ag15 i/o i/o ag16 i/o i/o ag17 i/o i/o ag18 i/o i/o ag19 i/o i/o ag20 i/o i/o ag21 i/o i/o ag22 i/o i/o ag23 i/o i/o ag24 i/o i/o ag25 i/o i/o ag26 i/o i/o ag27 gnd gnd ag28 rck rck ag29 v dd v dd ag30 i/o i/o ah1 gnd gnd ah2 i/o i/o ah3 v dd v dd ah4 i/o i/o ah5 v ddp v ddp ah6 i/o i/o ah7 i/o i/o ah8 i/o i/o ah9 i/o i/o ah10 i/o i/o ah11 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function ah12 i/o i/o ah13 i/o i/o ah14 i/o i/o ah15 i/o i/o ah16 i/o i/o ah17 i/o i/o ah18 i/o i/o ah19 i/o i/o ah20 i/o i/o ah21 i/o i/o ah22 i/o i/o ah23 i/o i/o ah24 i/o i/o ah25 i/o i/o ah26 v ddp v ddp ah27 tdi tdi ah28 v dd v dd ah29 v pp v pp ah30 gnd gnd aj1 gnd gnd aj2 gnd gnd aj3 i/o i/o aj4 v dd v dd aj5 i/o i/o aj6 v dd v dd aj7 i/o i/o aj8 i/o i/o aj9 i/o i/o aj10 i/o i/o aj11 i/o i/o aj12 i/o i/o aj13 i/o i/o aj14 i/o i/o aj15 i/o i/o aj16 i/o i/o aj17 i/o i/o aj18 i/o i/o aj19 i/o i/o aj20 i/o i/o 896 fbga pin (continued) pin number apa750 function apa1000 function
proasic plus family flash fpgas 108 advanced v0.6 aj21 i/o i/o aj22 i/o i/o aj23 i/o i/o aj24 i/o i/o aj25 v dd v dd aj26 i/o i/o aj27 v dd v dd aj28 tms tms aj29 gnd gnd aj30 gnd gnd ak2 gnd gnd ak3 gnd gnd ak4 i/o i/o ak5 gnd gnd ak6 i/o i/o ak7 gnd gnd ak8 i/o i/o ak9 i/o i/o ak10 i/o i/o ak11 i/o i/o ak12 i/o i/o ak13 i/o i/o ak14 i/o i/o ak15 i/o i/o ak16 i/o i/o ak17 i/o i/o ak18 i/o i/o ak19 i/o i/o ak20 i/o i/o ak21 i/o i/o ak22 i/o i/o ak23 i/o i/o ak24 gnd gnd ak25 i/o i/o ak26 gnd gnd ak27 i/o i/o ak28 gnd gnd ak29 gnd gnd 896 fbga pin (continued) pin number apa750 function apa1000 function
advanced v0.6 109 proasic plus family flash fpgas package pin assignments (continued) 1152-pin fbga (bottom view) a1 ball pad corner a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 ag ah aj ap ak al am an 31 32 33 34
proasic plus family flash fpgas 110 advanced v0.6 1152-pin fbga pin number apa1000 function a2 nc a3 gnd a4 gnd a5 gnd a6 i/o a7 v dd a8 v dd a9 v dd a10 v dd a11 i/o a12 gnd a13 i/o a14 v ddp a15 v ddp a16 i/o a17 gnd a18 gnd a19 i/o a20 v ddp a21 v ddp a22 i/o a23 gnd a24 i/o a25 v dd a26 v dd a27 v dd a28 v dd a29 i/o a30 gnd a31 gnd a32 gnd a33 nc b1 nc b2 nc b3 gnd b4 gnd b5 gnd b6 nc b7 i/o b8 nc b9 i/o b10 nc b11 i/o b12 gnd b13 i/o b14 v ddp b15 v ddp b16 i/o b17 gnd b18 gnd b19 i/o b20 v ddp b21 v ddp b22 i/o b23 gnd b24 i/o b25 nc b26 i/o b27 nc b28 i/o b29 nc b30 gnd b31 gnd b32 gnd b33 nc b34 nc c1 gnd c2 gnd c3 nc c4 gnd c5 gnd c6 i/o c7 gnd c8 i/o c9 gnd c10 i/o c11 i/o c12 i/o c13 i/o c14 i/o c15 i/o c16 i/o c17 i/o c18 i/o c19 i/o c20 i/o c21 i/o c22 i/o c23 i/o c24 i/o 1152-pin fbga pin number apa1000 function c25 i/o c26 gnd c27 i/o c28 gnd c29 i/o c30 gnd c31 gnd c32 nc c33 gnd c34 gnd d1 gnd d2 gnd d3 gnd d4 gnd d5 i/o d6 v dd d7 i/o d8 v dd d9 i/o d10 i/o d11 i/o d12 i/o d13 i/o d14 i/o d15 i/o d16 i/o d17 i/o d18 i/o d19 i/o d20 i/o d21 i/o d22 i/o d23 i/o d24 i/o d25 i/o d26 i/o d27 v dd d28 i/o d29 v dd d30 i/o d31 gnd d32 gnd d33 gnd d34 gnd e1 gnd 1152-pin fbga pin number apa1000 function e2 gnd e3 gnd e4 i/o e5 v dd e6 i/o e7 v ddp e8 i/o e9 i/o e10 i/o e11 i/o e12 i/o e13 i/o e14 i/o e15 i/o e16 i/o e17 i/o e18 i/o e19 i/o e20 i/o e21 i/o e22 i/o e23 i/o e24 i/o e25 i/o e26 i/o e27 i/o e28 v ddp e29 i/o e30 v dd e31 i/o e32 gnd e33 gnd e34 gnd f1 i/o f2 nc f3 i/o f4 v dd f5 i/o f6 gnd f7 i/o f8 i/o f9 i/o f10 i/o f11 i/o f12 i/o 1152-pin fbga pin number apa1000 function
advanced v0.6 111 proasic plus family flash fpgas f13 i/o f14 i/o f15 i/o f16 i/o f17 i/o f18 i/o f19 i/o f20 i/o f21 i/o f22 i/o f23 i/o f24 i/o f25 i/o f26 i/o f27 i/o f28 i/o f29 gnd f30 i/o f31 v dd f32 i/o f33 nc f34 nc g1 v dd g2 i/o g3 gnd g4 i/o g5 v ddp g6 i/o g7 v dd g8 i/o g9 v ddp g10 i/o g11 i/o g12 i/o g13 i/o g14 i/o g15 i/o g16 i/o g17 i/o g18 i/o g19 i/o g20 i/o g21 i/o g22 i/o g23 i/o 1152-pin fbga pin number apa1000 function g24 i/o g25 i/o g26 v ddp g27 i/o g28 v dd g29 i/o g30 v ddp g31 i/o g32 gnd g33 i/o g34 v dd h1 v dd h2 nc h3 i/o h4 v dd h5 i/o h6 i/o h7 i/o h8 gnd h9 i/o h10 i/o h11 i/o h12 i/o h13 i/o h14 i/o h15 i/o h16 i/o h17 i/o h18 i/o h19 i/o h20 i/o h21 i/o h22 i/o h23 i/o h24 i/o h25 i/o h26 i/o h27 gnd h28 i/o h29 i/o h30 i/o h31 v dd h32 i/o h33 nc h34 v dd 1152-pin fbga pin number apa1000 function j1 v dd j2 i/o j3 gnd j4 i/o j5 i/o j6 i/o j7 v ddp j8 i/o j9 v dd j10 i/o j11 v ddp j12 i/o j13 i/o j14 i/o j15 i/o j16 i/o j17 i/o j18 i/o j19 i/o j20 i/o j21 i/o j22 i/o j23 i/o j24 v ddp j25 i/o j26 v dd j27 i/o j28 v ddp j29 i/o j30 i/o j31 i/o j32 gnd j33 i/o j34 v dd k1 v dd k2 nc k3 i/o k4 i/o k5 i/o k6 i/o k7 i/o k8 i/o k9 i/o k10 gnd k11 i/o 1152-pin fbga pin number apa1000 function k12 i/o k13 i/o k14 i/o k15 i/o k16 i/o k17 i/o k18 i/o k19 i/o k20 i/o k21 i/o k22 i/o k23 i/o k24 i/o k25 gnd k26 i/o k27 i/o k28 i/o k29 i/o k30 i/o k31 i/o k32 i/o k33 nc k34 v dd l1 i/o l2 i/o l3 i/o l4 i/o l5 i/o l6 i/o l7 i/o l8 i/o l9 v ddp l10 i/o l11 v dd l12 i/o l13 i/o l14 i/o l15 i/o l16 i/o l17 i/o l18 i/o l19 i/o l20 i/o l21 i/o l22 i/o 1152-pin fbga pin number apa1000 function
proasic plus family flash fpgas 112 advanced v0.6 l23 i/o l24 v dd l25 i/o l26 v ddp l27 i/o l28 i/o l29 i/o l30 i/o l31 i/o l32 i/o l33 i/o l34 i/o m1 gnd m2 gnd m3 i/o m4 i/o m5 i/o m6 i/o m7 i/o m8 i/o m9 i/o m10 i/o m11 i/o m12 v dd m13 i/o m14 v ddp m15 v ddp m16 v ddp m17 v ddp m18 v ddp m19 v ddp m20 v ddp m21 v ddp m22 i/o m23 v dd m24 i/o m25 i/o m26 i/o m27 i/o m28 i/o m29 i/o m30 i/o m31 i/o m32 i/o m33 gnd 1152-pin fbga pin number apa1000 function m34 gnd n1 i/o n2 i/o n3 i/o n4 i/o n5 i/o n6 i/o n7 i/o n8 i/o n9 i/o n10 i/o n11 i/o n12 i/o n13 v dd n14 v dd n15 v dd n16 v dd n17 v dd n18 v dd n19 v dd n20 v dd n21 v dd n22 v dd n23 i/o n24 i/o n25 i/o n26 i/o n27 i/o n28 i/o n29 i/o n30 i/o n31 i/o n32 i/o n33 i/o n34 i/o p1 v ddp p2 v ddp p3 i/o p4 i/o p5 i/o p6 i/o p7 i/o p8 i/o p9 i/o p10 i/o 1152-pin fbga pin number apa1000 function p11 i/o p12 v ddp p13 v dd p14 gnd p15 gnd p16 gnd p17 gnd p18 gnd p19 gnd p20 gnd p21 gnd p22 v dd p23 v ddp p24 i/o p25 i/o p26 i/o p27 i/o p28 i/o p29 i/o p30 i/o p31 i/o p32 i/o p33 v ddp p34 v ddp r1 v ddp r2 v ddp r3 i/o r4 i/o r5 i/o r6 i/o r7 i/o r8 i/o r9 i/o r10 i/o r11 i/o r12 v ddp r13 v dd r14 gnd r15 gnd r16 gnd r17 gnd r18 gnd r19 gnd r20 gnd r21 gnd 1152-pin fbga pin number apa1000 function r22 v dd r23 v ddp r24 i/o r25 i/o r26 i/o r27 i/o r28 i/o r29 i/o r30 i/o r31 i/o r32 i/o r33 v ddp r34 v ddp t1 i/o t2 i/o t3 i/o t4 i/o t5 i/o t6 i/o t7 i/o t8 i/o t9 i/o t10 i/o t11 i/o t12 v ddp t13 v dd t14 gnd t15 gnd t16 gnd t17 gnd t18 gnd t19 gnd t20 gnd t21 gnd t22 v dd t23 v ddp t24 i/o t25 i/o t26 i/o t27 i/o t28 i/o t29 i/o t30 i/o t31 i/o t32 i/o 1152-pin fbga pin number apa1000 function
advanced v0.6 113 proasic plus family flash fpgas t33 i/o t34 i/o u1 gnd u2 gnd u3 i/o u4 i/o u5 agnd u6 npecl u7 gl u8 i/o u9 i/o u10 i/o u11 i/o u12 v ddp u13 v dd u14 gnd u15 gnd u16 gnd u17 gnd u18 gnd u19 gnd u20 gnd u21 gnd u22 v dd u23 v ddp u24 i/o u25 i/o u26 i/o u27 i/o u28 i/o u29 npecl u30 agnd u31 i/o u32 i/o u33 gnd u34 gnd v1 gnd v2 gnd v3 i/o v4 avdd v5 gl v6 ppecl v7 i/o v8 i/o v9 i/o 1152-pin fbga pin number apa1000 function v10 i/o v11 i/o v12 v ddp v13 v dd v14 gnd v15 gnd v16 gnd v17 gnd v18 gnd v19 gnd v20 gnd v21 gnd v22 v dd v23 v ddp v24 i/o v25 i/o v26 i/o v27 i/o v28 ppecl v29 gl v30 gl v31 avdd v32 i/o v33 gnd v34 gnd w1 i/o w2 i/o w3 i/o w4 i/o w5 i/o w6 i/o w7 i/o w8 i/o w9 i/o w10 i/o w11 i/o w12 v ddp w13 v dd w14 gnd w15 gnd w16 gnd w17 gnd w18 gnd w19 gnd w20 gnd 1152-pin fbga pin number apa1000 function w21 gnd w22 v dd w23 v ddp w24 i/o w25 i/o w26 i/o w27 i/o w28 i/o w29 i/o w30 i/o w31 i/o w32 i/o w33 i/o w34 i/o y1 v ddp y2 v ddp y3 i/o y4 i/o y5 i/o y6 i/o y7 i/o y8 i/o y9 i/o y10 i/o y11 i/o y12 v ddp y13 v dd y14 gnd y15 gnd y16 gnd y17 gnd y18 gnd y19 gnd y20 gnd y21 gnd y22 v dd y23 v ddp y24 i/o y25 i/o y26 i/o y27 i/o y28 i/o y29 i/o y30 i/o y31 i/o 1152-pin fbga pin number apa1000 function y32 i/o y33 v ddp y34 v ddp aa1 v ddp aa2 v ddp aa3 i/o aa4 i/o aa5 i/o aa6 i/o aa7 i/o aa8 i/o aa9 i/o aa10 i/o aa11 i/o aa12 v ddp aa13 v dd aa14 gnd aa15 gnd aa16 gnd aa17 gnd aa18 gnd aa19 gnd aa20 gnd aa21 gnd aa22 v dd aa23 v ddp aa24 i/o aa25 i/o aa26 i/o aa27 i/o aa28 i/o aa29 i/o aa30 i/o aa31 i/o aa32 i/o aa33 v ddp aa34 v ddp ab1 i/o ab2 i/o ab3 i/o ab4 i/o ab5 i/o ab6 i/o ab7 i/o ab8 i/o 1152-pin fbga pin number apa1000 function
proasic plus family flash fpgas 114 advanced v0.6 ab9 i/o ab10 i/o ab11 i/o ab12 i/o ab13 v dd ab14 v dd ab15 v dd ab16 v dd ab17 v dd ab18 v dd ab19 v dd ab20 v dd ab21 v dd ab22 v dd ab23 i/o ab24 i/o ab25 i/o ab26 i/o ab27 i/o ab28 i/o ab29 i/o ab30 i/o ab31 i/o ab32 i/o ab33 i/o ab34 i/o ac1 gnd ac2 gnd ac3 i/o ac4 i/o ac5 i/o ac6 i/o ac7 i/o ac8 i/o ac9 i/o ac10 i/o ac11 i/o ac12 v dd ac13 i/o ac14 v ddp ac15 v ddp ac16 v ddp ac17 v ddp ac18 v ddp ac19 v ddp 1152-pin fbga pin number apa1000 function ac20 v ddp ac21 v ddp ac22 i/o ac23 v dd ac24 i/o ac25 i/o ac26 i/o ac27 i/o ac28 i/o ac29 i/o ac30 i/o ac31 i/o ac32 i/o ac33 gnd ac34 gnd ad1 i/o ad2 i/o ad3 i/o ad4 i/o ad5 i/o ad6 i/o ad7 i/o ad8 i/o ad9 v ddp ad10 i/o ad11 v dd ad12 i/o ad13 i/o ad14 i/o ad15 i/o ad16 i/o ad17 i/o ad18 i/o ad19 i/o ad20 i/o ad21 i/o ad22 i/o ad23 i/o ad24 v dd ad25 i/o ad26 v ddp ad27 i/o ad28 i/o ad29 i/o ad30 i/o 1152-pin fbga pin number apa1000 function ad31 i/o ad32 i/o ad33 i/o ad34 i/o ae1 v dd ae2 nc ae3 i/o ae4 i/o ae5 i/o ae6 i/o ae7 i/o ae8 i/o ae9 i/o ae10 gnd ae11 i/o ae12 i/o ae13 i/o ae14 i/o ae15 i/o ae16 i/o ae17 i/o ae18 i/o ae19 i/o ae20 i/o ae21 i/o ae22 i/o ae23 i/o ae24 i/o ae25 gnd ae26 i/o ae27 i/o ae28 i/o ae29 i/o ae30 i/o ae31 i/o ae32 i/o ae33 nc ae34 v dd af1 v dd af2 i/o af3 gnd af4 i/o af5 i/o af6 i/o af7 v ddp 1152-pin fbga pin number apa1000 function af8 i/o af9 v dd af10 i/o af11 v ddp af12 i/o af13 i/o af14 i/o af15 i/o af16 i/o af17 i/o af18 i/o af19 i/o af20 i/o af21 i/o af22 i/o af23 i/o af24 v ddp af25 tck af26 v dd af27 trst af28 v ddp af29 i/o af30 i/o af31 i/o af32 gnd af33 i/o af34 v dd ag1 v dd ag2 nc ag3 i/o ag4 v dd ag5 i/o ag6 i/o ag7 i/o ag8 gnd ag9 i/o ag10 i/o ag11 i/o ag12 i/o ag13 i/o ag14 i/o ag15 i/o ag16 i/o ag17 i/o ag18 i/o 1152-pin fbga pin number apa1000 function
advanced v0.6 115 proasic plus family flash fpgas ag19 i/o ag20 i/o ag21 i/o ag22 i/o ag23 i/o ag24 i/o ag25 i/o ag26 i/o ag27 gnd ag28 i/o ag29 i/o ag30 i/o ag31 v dd ag32 i/o ag33 nc ag34 v dd ah1 v dd ah2 i/o ah3 gnd ah4 i/o ah5 v ddp ah6 i/o ah7 v dd ah8 i/o ah9 v ddp ah10 i/o ah11 i/o ah12 i/o ah13 i/o ah14 i/o ah15 i/o ah16 i/o ah17 i/o ah18 i/o ah19 i/o ah20 i/o ah21 i/o ah22 i/o ah23 i/o ah24 i/o ah25 i/o ah26 v ddp ah27 i/o ah28 v dd ah29 tdo 1152-pin fbga pin number apa1000 function ah30 v ddp ah31 vpn ah32 gnd ah33 i/o ah34 v dd aj1 i/o aj2 nc aj3 i/o aj4 v dd aj5 i/o aj6 gnd aj7 i/o aj8 i/o aj9 i/o aj10 i/o aj11 i/o aj12 i/o aj13 i/o aj14 i/o aj15 i/o aj16 i/o aj17 i/o aj18 i/o aj19 i/o aj20 i/o aj21 i/o aj22 i/o aj23 i/o aj24 i/o aj25 i/o aj26 i/o aj27 i/o aj28 i/o aj29 gnd aj30 rck aj31 v dd aj32 i/o aj33 nc aj34 nc ak1 gnd ak2 gnd ak3 gnd ak4 i/o ak5 v dd ak6 i/o 1152-pin fbga pin number apa1000 function ak7 v ddp ak8 i/o ak9 i/o ak10 i/o ak11 i/o ak12 i/o ak13 i/o ak14 i/o ak15 i/o ak16 i/o ak17 i/o ak18 i/o ak19 i/o ak20 i/o ak21 i/o ak22 i/o ak23 i/o ak24 i/o ak25 i/o ak26 i/o ak27 i/o ak28 v ddp ak29 tdi ak30 v dd ak31 vpp ak32 gnd ak33 gnd ak34 gnd al1 gnd al2 gnd al3 gnd al4 gnd al5 i/o al6 v dd al7 i/o al8 v dd al9 i/o al10 i/o al11 i/o al12 i/o al13 i/o al14 i/o al15 i/o al16 i/o al17 i/o 1152-pin fbga pin number apa1000 function al18 i/o al19 i/o al20 i/o al21 i/o al22 i/o al23 i/o al24 i/o al25 i/o al26 i/o al27 v dd al28 i/o al29 v dd al30 tms al31 gnd al32 gnd al33 gnd al34 gnd am1 gnd am2 gnd am3 nc am4 gnd am5 gnd am6 i/o am7 gnd am8 i/o am9 gnd am10 i/o am11 i/o am12 i/o am13 i/o am14 i/o am15 i/o am16 i/o am17 i/o am18 i/o am19 i/o am20 i/o am21 i/o am22 i/o am23 i/o am24 i/o am25 i/o am26 gnd am27 i/o am28 gnd 1152-pin fbga pin number apa1000 function
proasic plus family flash fpgas 116 advanced v0.6 am29 i/o am30 gnd am31 gnd am32 nc am33 gnd am34 gnd an1 nc an2 nc an3 gnd an4 gnd an5 gnd an6 nc an7 i/o an8 nc an9 i/o an10 nc an11 i/o an12 gnd an13 i/o an14 v ddp an15 v ddp an16 i/o an17 gnd an18 gnd an19 i/o an20 v ddp an21 v ddp an22 i/o an23 gnd an24 i/o an25 nc an26 i/o an27 nc an28 i/o an29 nc an30 gnd an31 gnd an32 gnd an33 nc an34 nc ap2 nc ap3 gnd ap4 gnd ap5 gnd ap6 i/o 1152-pin fbga pin number apa1000 function ap7 v dd ap8 v dd ap9 v dd ap10 v dd ap11 i/o ap12 gnd ap13 i/o ap14 v ddp ap15 v ddp ap16 i/o ap17 gnd ap18 gnd ap19 i/o ap20 v ddp ap21 v ddp ap22 i/o ap23 gnd ap24 i/o ap25 v dd ap26 v dd ap27 v dd ap28 v dd ap29 i/o ap30 gnd ap31 gnd ap32 gnd ap33 nc 1152-pin fbga pin number apa1000 function
advanced v0.6 117 proasic plus family flash fpgas list of changes the following table lists critical changes that were made in the current version of the document. previous version changes in current version (advanced v0.6) page advanced v0.5 the description for the v pn pin has changed. page 54 advanced v0.4 the plastic device resources table on page 4 has been updated. page 4 figure 19 and figure 20 on page 28 have been updated. page 28 the tristate buffer delays table on page 30 has been updated. page 30 the output buffer delays table on page 31 has been updated. page 31 the input buffer delays table on page 32 has been updated. page 32 the global input buffer delays table on page 32 has been updated. page 32 the 456-pin pbga table on page 63 has been updated. page 63 the 676-fbga pin table on page 87 has been updated. page 87 advanced v0.3 the proasic plus product profile section on page 1 has been changed. page 1 the plastic device resources section on page 4 has been updated. page 4 the supply voltages table on page 10 has been updated. page 10 wdata has ben changed to di, and rdata has been changed to do to make them consistent with the signal names found in the macro library guide . figure 13 on page 15 and figure 14 on page 16 have been updated. page 15 and page 16 the design environment section on page 17 and figure 18 on page 18 have been updated. page 17 and page 18 the table in the package thermal characteristics section on page 19 has been updated. page 19 the calculating power dissipation section on page 20 is new. page 20 the programming and storage temperature limits section on page 22 is new. page 22 the supply voltages section on page 22 has been updated. page 22 the dc electrical specifications (v ddp = 2.5v +/-0.2v) section on page 23 was updated. page 23 the dc electrical specifications (v ddp = 3.3v +/-0.3v and vdd 2.5+/-0.2v) section on page 24 was updated. page 24 the ac specifications (3.3v pci revision 2.2 operation) section on page 26 was updated. page 26 the clock conditioning circuit section on page 27 was updated. page 27 figure 19 on page 28 was updated. page 28 figure 20 on page 28 is new. page 28 tables 5, 6, and 7 from advanced v0.3 were removed. the memory block sram interface signals section on page 35 was updated. page 35 the memory block fifo interface signals section on page 46 was updated. page 46 all pinout tables have been updated, and several packages are new: 208-pin pqfp apa150, apa300, apa450, apa600 456-pin pbga apa150, apa300, apa450, apa600 144-pin fbga apa150, apa300, apa450 256-pin fbga apa150, apa300, apa450, apa600 676-pin fbga apa600 advanced v0.1 figure 15 on page 16 has been updated page 16
proasic plus family flash fpgas 118 advanced v0.6 data sheet categories in order to provide the latest information to designers, some data sheets are published before data has been fully characterized. product briefs are modified versions of data sheets. data sheets are marked as ? advanced, ? ? preliminary, ? and ? web-only. ? the definition of these categories are as follows: product brief the product brief is a modified version of an advanced data sheet containing general product information. this brief summarizes specific device and family information for non-release products. advanced the data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but not for production. preliminary the data sheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. unmarked (production) the data sheet contains information that is considered to be final. web-only versions web-only versions have three numbers in the version number (example: v2.0.1). a web-only version means actel is posting the data sheet so customers have the latest information, but we are not printing the version because some information is going to change shortly after posting.

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